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  6. Example of 4Gsps signal processing using AD9213

Example of 4Gsps signal processing using AD9213

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RFSOC, AD9213 Design Example

last updated:Sep 28, 2026

Edic-Systems
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Directly from RF to zero IF. The AD9213 showcases a new frontier of 3.6GHz ultra-wideband reception and FPGA collaboration.

This introduces a system image that downconverts an input center frequency of 6.0 GHz with a bandwidth of 3.6 GHz (frequency range: 4.2 GHz to 7.8 GHz) using the internal NCO (6.0 GHz) of the AD9213 to Zero-IF (Zero-IF / quadrature complex conversion). It is a very advanced and rational frequency plan, illustrating the frequency transition image (spectrum movement) from direct RF sampling to Zero-IF conversion, as well as the consistency of the filter bandwidth for 1/2 decimation in a diagram.

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image_ed4a0af1.jpg

Example of 4Gsps signal processing using AD9213

image_ed4a0af1.jpg
image_ed4a0af1.jpg

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Input center frequency .......................... 6GHz Input bandwidth ................................... 3.6GBW ADC sampling frequency ........................ 8Gsps NCO frequency .................................... 6GHz Digital complex mixing Decimation ratio .................................. 1/2 JESD lane count ................................... 16Lane Bit depth ............................................. I/Q 32Bit JESD line rate ...................................... 10Gbps

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◆RF Input (4.2 ~ 7.8 GHz): An input signal centered at 6 GHz with a bandwidth of 3.6 GHz is mapped to the 1st Nyquist (centered at 2.0 GHz, inverted) through 8 GSPS sampling. ◆Digital Downconversion (NCO @ 6.0 GHz): The signal is pulled down to exactly 0 Hz (Zero-IF) using an internal NCO and mixer, and is restored and converted to a complex baseband (I/Q) signal (-1.8 GHz to +1.8 GHz). ◆1/2 Decimation & JESD Output: After passing through a half-band filter, the I/Q data at 4.0 GSPS is handed over to the FPGA's 250 MHz fabric logic via a 16-lane JESD interface (each 10.0 Gbps). ◆The internal CLK of the FPGA is 250 MHz, but by performing 16 parallel processing, a 4 GSPS digital signal processing system can be constructed.

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We provide comprehensive support from idea and specification proposals to development and manufacturing. We consistently design without interruption from analog front-end to high-speed digital, FPGA logic, and edge AI, building high-bandwidth, low-latency, and highly reliable electronic systems for IoT/communication, industrial equipment, broadcasting, measurement, and next-generation mobility. By integrating high-frequency design, signal processing, and real-time control, we ensure that the required specifications are met while proposing improvements where necessary, achieving a high level of completion in implementation.

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