1～14 item / All 14 items
Test chip with solder bumps
Test chip equipped with solder bumps □Product name ... JTEG Phase1E50/JTEG Phase1E28/JTEG Phase1E15 ■Main applications Material development, equipment development, substrate development, package development Process startup/development, promotional data acquisition, etc.
Test chip with solder bumps
Test chip equipped with solder bumps (narrow pitch area type) □Product name ... JTEG Phase2E200/JTEG Phase2E175/JTEG Phase2E150 ■Main applications Material development, equipment development, substrate development, package development Process startup/development, promotional data acquisition, etc.
Test chip for thermal resistance and stress measurement.
Thermal resistance and stress measurement test chip □Product name... JTEG Phase5/JTEG Phase5GB2 ■Main applications Material development, equipment development, package development Process startup/development, promotional data acquisition, etc.
Test chip for evaluating LCD driver implementation.
Liquid Crystal Driver Implementation Evaluation Test Chip □ Product Names ... JTEG Phase6_50/JTEG Phase6_35 JTEG Phase6_30/JTEG Phase6_25 JTEG Phase6_15S/JTEG Phase6_20 JTEG Phase6_40/JTEG Phase6_25E JTEG Phase6_60 ■ Main Applications Material development, equipment development, substrate development, process startup/development, promotional data acquisition, etc.
![Test chip [Large general-purpose]](https://image.mono.ipros.com/public/product/image/232/135151026/IPROS_18202600641364791000.gif?w=280&h=280)
Test chip [Large general-purpose]
General-purpose test chip with a larger chip size than JTEG Phase 0 ■ Wafer size ... 8-inch wafer ■ Base chip size ... 3.5mm × 3.5mm ■ Pad pitch ... 120μm ■ Number of pads ... 96 bumps (the inner pads do not have aluminum pads opened) ■ Compatible bump process ... gold stud bump ■ Compatible substrate ... none ■ Options ... bump mounting / dicing processing / back grinding processing ■ Main applications Material development, equipment development, package development Process startup/development, promotional data acquisition, etc.
![Test chip [for ultra fine pitch WB/FC mounting evaluation]](https://image.mono.ipros.com/public/product/image/e58/135151030/IPROS_16186590904543728000.gif?w=280&h=280)
Test chip for ultra-fine pitch WB/FC mounting evaluation.
Ultra Fine Pitch WB・FC Implementation Evaluation Test Chip ■Wafer Size ... 8-inch wafer ■Base Chip Size ... 6.0mm × 2.3mm ■Pad Pitch ... 300μm ■Number of Pads ... 16 bumps ■Compatible Bump Process ... None ■Compatible Substrate ... None ■Options ... Dicing processing / Back grinding processing ■Main Applications Material development, promotional data acquisition, etc.
![Test chip [for ultra fine pitch WB/FC mounting evaluation]](https://image.mono.ipros.com/public/product/image/54b/135151029/IPROS_15090265310453498000.gif?w=280&h=280)
Test chip for ultra-fine pitch WB/FC mounting evaluation.
Ultra Fine Pitch WB・FC Implementation Evaluation Test Chip □Product Name... JTEG Phase11_80/JTEG Phase11_70/JTEG Phase11_60/JTEG Phase11_50/JTEG Phase11_40 ■Main Applications Package development, process startup/development, promotional data acquisition, etc.
Test Chip 【Multi-Type】
Fine pitch wire bonding, gold-plated bumps, gold stud bumps, and multi-purpose test chip ■ Wafer size: 6-inch wafer ■ Base chip size: 2.11mm × 2.11mm ■ Pad pitch: 45, 50, 60μm from the chip inner peripheral pads ■ Number of pads: 92, 92, 100 pads from the chip inner peripheral pads ■ Compatible bump processes: Gold-plated bumps (select one type from pads with 45, 50, 60μm pitch) / Gold stud bumps ■ Compatible substrates: None ■ Options: Dicing processing / Back grinding processing ■ Main applications Material development, equipment development, substrate development Process startup/development, promotional data acquisition, etc.
Test chip 【Ultra-small chip size 0.55mm】
Ultra-small chip size 0.55mm□ test chip ■ Wafer size ... 6-inch wafer ■ Base chip size ... 0.55mm × 0.55mm□ ■ Pad pitch ... 110μm ■ Number of pads ... 8 pads ■ Compatible bump processes ... Gold-plated bump / Gold stud bump ■ Options ... Bump mounting / Dicing processing / Back grinding processing / Surface polyimide film formation (excluding gold-plated bump products) ■ Main applications Material development, equipment development, package development Process startup/development, promotional data acquisition, etc.
Test chip for evaluating Cu bonding with Cu bumps.
Cu bump mounted Cu bonding evaluation test chip ■Wafer size ... 8-inch wafer ■Base chip size ... 5.09mm × 5.09mm ■Pad pitch ... 150μm (staggered pads) ■Number of pads ... 841 bumps ■Compatible bump process ... Cu bump ■Compatible substrate ... None ■Options ... Bump mounting / Dicing processing / Back grinding processing ■Main applications Package development, process startup/development, promotional data acquisition, etc.
Test chip with next-generation solder bumps.
Next-generation test chip with Low-K film used in the interlayer dielectric layer for solder bumps ■Wafer size: 8-inch wafer ■Base chip size: 5.02mm × 5.02mm ■Pad pitch: 200μm (staggered pads) ■Number of pads: 484 bumps ■Compatible bump processes: Eutectic solder / Lead-free solder ■Compatible substrate: JKIT Type 5 ■Options: Bump mounting / Dicing processing / Back grinding processing / Surface polyimide film formation ■Main applications: Package development, process ramp-up / Development, promotional data acquisition, etc.
Glass chip for observing underfill entrapment voids.
Underfill Encapsulation Void Observation Glass Chip ■Wafer Size: 5-inch Wafer ■Base Chip Size: 5.02mm × 5.02mm ■Pad Pitch: 200μm ■Number of Pads: 484 Bumps ■Compatible Bump Processes: Eutectic Solder / Lead-Free Solder ■Compatible Substrates: JKIT Type1 (SIDE A) / JKIT Type5 ■Base Material: Natural Quartz Glass ■Options: Bump Mounting / Dicing Processing ■Main Applications: Material Development, Process Startup/Verification, Promotional Data Acquisition, etc.
Test chip for ultra-fine pitch wire bonding evaluation.
Super Fine Pitch Wire Bonding Evaluation Test Chip ■Wafer Size: 8-inch wafer ■Base Chip Size: 3.0mm × 3.0mm ■Pad Pitch: 30, 35, 40, 45, 50, 55, 60μm from the chip inner peripheral pads ■Number of Pads: 120, 136, 144, 152, 152, 160, 160 pads from the chip inner peripheral pads ■Compatible Bump Process: None ■Compatible Substrate: None ■Options: Dicing processing / Back grinding processing ■Main Applications Material development, equipment development, package development Process startup/development, promotional data acquisition, etc.
![Test chip [Multi-type]](https://image.mono.ipros.com/public/product/image/086/135151018/IPROS_13072303327799126000.gif?w=280&h=280)
Test Chip 【Multi-Type】
Test chip used for wire bonding, gold-plated bumps, gold stud bumps, and multi-purpose applications. ■Wafer size: 6-inch wafer ■Base chip size: 2.13×2.1mm ■Pad pitch: 130μm ■Number of pads: 108 bumps (48 bumps on the inner circumference, 60 bumps on the outer circumference) ■Compatible bump processes: Gold-plated bumps / Gold stud bumps ■Compatible substrate: JKIT Type2 (SIDE A) ■Options: Bump mounting / Dicing processing / Back grinding processing / Surface polyimide film formation (excluding gold-plated bump products) / Can be changed to gallium arsenide wafer (only for gold-plated bump products) ■Main applications: Material development, equipment development, substrate development, package development, process startup/development, promotional data acquisition, etc.
