Last Updated： Aggregation Period:Jul 23, 2025～Aug 19, 2025
This ranking is based on the number of page views on our site.
Last Updated： Aggregation Period:Jul 23, 2025～Aug 19, 2025
This ranking is based on the number of page views on our site.
Last Updated： Aggregation Period:Jul 23, 2025～Aug 19, 2025
This ranking is based on the number of page views on our site.
31～45 item / All 81 items
By connecting with "SLIPHDMIR," it is possible to most efficiently extract performance and characteristics.
SLISHDMIR is an IP core for HDMI receiver link compliant with the HDMI 1.3a standard.
Achieving a maximum transfer rate of 300MB/s for UHS-II with low power consumption through proprietary technology.
This is a PHY IP solution for the ultra-high-speed interface "UHS-II" that can be used with the new SD card standards SDXC and SDHC.
Error correction code with the option to add bit/byte interleaving function.
The "Reed-Solomon Encoder/Decoder" is an IP core for error correction coding/decoding using the Reed-Solomon method, which is used to improve communication quality in a wide range of fields such as wireless devices, xDSL modems, and digital TVs. It supports variable data block lengths. 【Features】 ■ Supports variable data block lengths ■ The number of check bits, primitive polynomial, and generator polynomial can be customized according to your requirements ■ Additional bit/byte interleaving functionality is also possible *For more details, please refer to the PDF document or feel free to contact us.
Achieving 10 times faster 10GbE TCP/IP communication functionality with pure hardware logic without CPU!
The 10GbE TCP Offloading Engine IP Core (TOE10G-IP) is a groundbreaking solution that allows complex TCP transmission and reception processing, which traditionally required expensive high-end CPUs, to be implemented solely with pure hardware logic without a CPU. It comes standard with a reference design compatible with Xilinx/Intel FPGAs, which can help shorten product development time.
You can implement TCP/IP communication functionality with pure hardware logic without a CPU!
The TCP Offloading Engine IP Core (TOE1G-IP) is a groundbreaking solution that enables the complex TCP transmission and reception processes, which traditionally required expensive high-end CPUs, to be implemented solely with pure hardware logic without a CPU. It comes standard with a reference design compatible with Xilinx/Altera FPGAs, which can help shorten product development time.
With the USB3.0 IP core, it is possible to develop a highly versatile FAT32 data recorder in a short period of time!
The 【USB3.0-IP】 complies with the USB3.0 standard Revision 1.0 and includes both the link layer and protocol layer, making it easy to implement a USB3.0 interface when combined with an external PHY chip from TI. A reference design compatible with Xilinx/Altera FPGAs is included as standard with the core product, which can help shorten product development time.
Achieving 40 times speed 10GbE TCP/IP communication functionality with pure hardware logic without CPU!
The 40GbE TCP Offloading Engine IP Core (TOE40G-IP) is a groundbreaking solution that enables the complex TCP transmission and reception processes, which traditionally required expensive high-end CPUs, to be implemented solely with pure hardware logic without a CPU. It comes standard with a reference design compatible with Xilinx/Intel FPGAs, which can help shorten product development time.
Providing high-quality and high-performance IP core products for the storage industry! Supporting the development of ASSP products as well.
IntelliProp develops high-quality and high-performance IP core products and ASSP products for the storage industry. Since its establishment in 1998, the company has been providing competitive IP core products as a leading company in specialized fields such as SATA, SAS, PCIe/NVMe, NAND flash, security/encryption, and RAID technology in Longmont, Colorado, USA, where major companies in the storage industry gather. *For more details, please refer to the PDF document or feel free to contact us.*
High quality, low latency, power-saving IP Core
Providing a group of MPEG standard codecs as IP Cores with high quality, low latency, low power consumption, and a small footprint. Available in Intel FPGA and Xilinx versions.
Various FPGA-compatible IP! Compatible with "SY-OP-09" and equipped with master functionality.
We would like to introduce our product, 'SYRXIC5'. This is an IP for various FPGAs. It is compatible with "SY-OP-09" and comes with a master function. Additionally, we provide boards, FPGAs, and software to accelerate development and evaluation. Please feel free to contact us when you need assistance. 【Products We Handle (Partial)】 ■SY-M3-01 ■SY-M3-03 ■SY-M3-04 ■SY-AN-05 ■SY-OP-06 *For more details, please refer to the PDF document or feel free to contact us.
An IP core that addresses network packet loss and ordering!
The "IP_SMPTE2022_Video" is an IP core compliant with SMPTE2022-5/6/7. It can handle multiple port inputs or outputs of 20-bit parallel data for 3G/HD. Additionally, changes on the line side are possible. It can support 10GbE/25GbE/40GbE (10GbE×4)/100GbE (25GbE×4), among others. 【Features】 ■ Error correction function using FEC compliant with SMPTE2022-5-2007 ■ MAC/IP/UDP/RTP filtering ■ Support for both IPv4 and IPv6 ■ Capability to include ARP ■ Hitless support compliant with SMPTE2022-7 (Hitless compatible) *For more details, please download the PDF or feel free to contact us.
By simply writing image data, high-speed transmission of video can be achieved!
Our "CoaXpress(R) Camera-side IP Core" is an IP core compliant with the industrial camera interface CoaXpress V1.1. This product uses coaxial cables, achieving a performance of 25Gbps (effective 20Gbps) by utilizing up to four cables, each capable of 6.25Gbps (effective 5Gbps). The cables can be extended up to several tens to 100 meters, allowing for the placement of the camera further away from the PC used for video capture, thereby increasing the flexibility of equipment installation. 【Features】 - Supports stream packet transmission, control packet transmission/reception, and trigger reception functions. - Transmission is possible without a frame buffer due to the idle word insertion function. - The use of a high-speed serializer within the FPGA allows for miniaturization of the device. - Minimal footprint (approximately 1000 slices per lane on Kintex-7). - Link speeds can be dynamically changed from 1.25Gbps to 6.25Gbps. - Supports from 1 lane (effective 5Gbps) to 4 lanes (effective 20Gbps). *For more details, please download the PDF or feel free to contact us.
A hardware/firmware library for PTP is available, allowing PTP functionality to be implemented with inexpensive FPGAs and Ethernet PHYs.
This product is an IP core compliant with the industrial camera interface GigE Vision V2.0. It hardware-accelerates the image transmission function that requires high-speed transfer, while other slower processing is handled by the firmware of the FPGA's internal processor. Additionally, the firmware library is provided in C source code, allowing for modifications and additions of functions as needed. Furthermore, it supports PTP/IEEE1588 adopted in GigE Vision 2.0. This feature does not require any special external Ethernet PHY or MAC. 【Features】 ■ GVSP function: In addition to essential core functions, it supports Chunk Data ■ Supports PTP/IEEE1588 ■ Firmware supports not only slave but also simple master functionality ■ Comes with a reference design that operates as a GigE Vision camera ■ Measures PTP error while performing image transfer at 4000x3000x9.5fps *For more details, please refer to the PDF document or feel free to contact us.
