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IP Cores Product List and Ranking from 29 Manufacturers, Suppliers and Companies | IPROS GMS

Last Updated： Aggregation Period:Feb 04, 2026～Mar 03, 2026
This ranking is based on the number of page views on our site.

IP Cores Manufacturer, Suppliers and Company Rankings

Last Updated： Aggregation Period:Feb 04, 2026～Mar 03, 2026
This ranking is based on the number of page views on our site.

  1. 富士ソフト インダストリービジネス事業部 Kanagawa//software
  2. デザイン・ゲートウェイ Tokyo//Electronic Components and Semiconductors
  3. Euresys Japan ユレシス　ジャパン Kanagawa//Electronic Components and Semiconductors
  4. 4 サイレックス・テクノロジー Kyoto//Other manufacturing
  5. 5 ネットワークアディションズ Kanagawa//IT/Telecommunications
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IP Cores Product ranking

Last Updated： Aggregation Period:Feb 04, 2026～Mar 03, 2026
This ranking is based on the number of page views on our site.

  1. Wireless LAN Survey "WM-100" サイレックス・テクノロジー
  2. TOE10G-IP core for FPGA デザイン・ゲートウェイ
  3. A system to notify when passing by to prevent forklift accidents in the factory. パシフィック湘南
  4. 4 IP core for FPGA/ASIC NVMe Target 富士ソフト インダストリービジネス事業部
  5. 5 JPEG compression IP core (Verilog) メティエ

IP Cores Product List

61～90 item / All 117 items

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NVMe-to-SATA Bridge

NVMe-to-SATA Bridge

Available for LBA remapping, data encryption, data compression, and endpoint aggregation!

We would like to introduce the 'NVMe-to-SATA Bridge' handled by Fujisoft Inc. This product is an IP core for creating an NVMe-to-SATA protocol bridge using NVMe Host IP core and SATA AHCI Host IP core. In this architecture, a sandbox area is implemented in the bridge, allowing for the implementation of custom logic and firmware. 【Specifications (Excerpt)】 ■ NVMe protocol interface complies with NVMe 1.4 standard ■ SATA interface complies with SATA 3.3 specification ■ Supports industry-standard AHCI (Advanced Host Controller Interface) v.1.3.1 ■ Compatible with third-party PCIe Root Complex IP cores ■ Supports automatic initialization using PCIe hard blocks *For more details, please download the PDF or feel free to contact us.

  • ASIC
  • IP Cores

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ECC with BCH Algorithm IP Core

ECC with BCH Algorithm IP Core

Configurable encoding/decoding block! Parallelized BCH encoder/decoder.

The "ECC with BCH Algorithm IP Core" is an IP core designed to add error detection/correction functionality using industry-standard BCH class error correction codes, preventing data loss or corruption over noisy and unreliable communication channels. If the BCH configuration is not covered, it can be customized to support a wide range of BCH codes. It can be used in a variety of applications, including data storage devices (SATA, SAS, FLASH), two-dimensional barcodes, satellite communication/telemetry, radio signal recording, wireless communication, high-speed modems such as ADSL and xDSL, and power line standards. 【Specifications】 ■ High bandwidth and low latency through parallel processing ■ Configurable encoding/decoding block structure ■ Configurable word length/block size ■ FIFO data interface of 32, 64, 128, or 256 ■ Parallelized BCH encoder/decoder *For more details, please download the PDF or feel free to contact us.

  • ASIC
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AES-XTS Encryption IP Core

AES-XTS Encryption IP Core

You can choose the AES encryption key from 128 or 256 bits! The encryption algorithm complies with FIPS-197.

We would like to introduce the 'AES-XTS Encryption IP Core' that we handle. This product is an AES-XTS encryption IP core that enables full disk encryption for storage devices. It supports AES-XTS encryption levels of 128-bit or 256-bit and allows encryption tailored to data transfer rates of SATA 6Gbps, SAS 12Gbps, and PCIe (NVMe) Gen4 x4 lanes. 【Specifications】 ■ FIPS-197 compliant AES-XTS algorithm ■ AES encryption key selectable from 128 or 256 bits ■ Configurable number of encoding/decoding pipelines ■ Independent management of encryption/decryption keys ■ Simultaneous support for encoding and decoding ■ Supports integer multiples of 16-byte data unit sizes *For more details, please download the PDF or feel free to contact us.

  • ASIC
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PTP network tool 'dadBerry-TOOLs'

PTP network tool 'dadBerry-TOOLs'

Build a visual and efficient evaluation, verification, and operational environment within the PTP network.

It is an evaluation, verification, and operation tool that conforms to the IEEE1588 standard PTP network and is used on Windows PCs. It consists of configure (configuration settings), state viewer (status display), sync viewer (synchronization accuracy display), among others, and has high versatility. It can be used in network systems with multi-vendor configurations.

  • Other network tools
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PTP network clock "dadBerry-100"

PTP network clock "dadBerry-100"

You can connect to the PTP network to check the accurate time and the normal/abnormal operation of PTP.

An environment has been developed to provide high-precision time information within the network. This time information is mainly used for the synchronized operation of devices and equipment. Currently, it is rare for humans to receive this information. However, in specific business applications, there may be cases where the existing time synchronization features, which allow for second-level errors, are not acceptable. This product displays the time within a PTP network. Since it shows time information from a GPS-synchronized grandmaster, it provides extremely accurate values. Regular time adjustments are also unnecessary. Additionally, it monitors the normal/abnormal operation of PTP. It can be utilized for the primary analysis of issues that occur within the PTP network. This product complies with the international standard IEEE1588-2008.

  • Other network tools
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PTP software for RX family 'pwDadBerry-FRX'

PTP software for RX family 'pwDadBerry-FRX'

We will implement it on Renesas Electronics' RX microcontrollers to build various sensor networks.

The RX64M (manufactured by Renesas Electronics), equipped with IEEE1588 functionality, is a device that easily enables daisy chain wiring. By implementing our PTP software on the RX64M, which has two Ethernet ports, it can also function as a BC (Boundary Clock). Synchronization signals of 51.2KHz, 102.4KHz, 204.8KHz, 409.6KHz, and 819.2KHz, necessary for sensor control, are generated using a PLD. Please realize the construction of various sensor networks that leverage the features of the RX microcontroller capable of daisy chain configuration through the implementation of PTP software for the RX family.

  • Other embedded systems (software and hardware)
  • IP Cores

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FM broadcasting synchronous transmission device 'RFD Sync-A300'

FM broadcasting synchronous transmission device 'RFD Sync-A300'

A digital audio transmission device capable of FM synchronization has been developed for radio broadcasting operators using ISDN services, which are scheduled to end in January 2024.

In 2024, the main synchronization means of the public circuit network will be discontinued. NTT has announced that it will end the provision of ISDN services in January 2024. With the termination of ISDN services, network synchronization (clock) signals will no longer be available, so we must prepare something new to replace the network synchronization signals. Radio broadcasting operators currently using ISDN services are encouraged to consider the digital audio synchronization transmission device 'RFD Sync-A300', which can utilize IP packet communication networks (fiber optic services).

  • Other network tools
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Wireless communication device design services

Wireless communication device design services

Leave everything from system and circuit design to prototype production to us.

Our company can provide consistent initial development from system and circuit design to prototype fabrication for wireless communication devices, tailored to customer requests and the resources provided. We place great importance on "design quality," considering not only the standards and performance based on radio laws as a wireless communication device but also the application, structure, and noise resistance, aiming for development and design that will serve as a foundation for mass production. Please feel free to consult us with your requests. 【Deliverables】 ■ Hardware system requirements specification ■ Reference circuit ■ Specification of key devices *For more details, please download the PDF (company brochure) or feel free to contact us.

  • Contract manufacturing
  • Mechanical Design
  • IP Cores

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Development Support Board, Module, IP: SYRXIC5

Development Support Board, Module, IP: SYRXIC5

Various FPGA-compatible IP! Compatible with "SY-OP-09" and equipped with master functionality.

We would like to introduce our product, 'SYRXIC5'. This is an IP for various FPGAs. It is compatible with "SY-OP-09" and comes with a master function. Additionally, we provide boards, FPGAs, and software to accelerate development and evaluation. Please feel free to contact us when you need assistance. 【Products We Handle (Partial)】 ■SY-M3-01 ■SY-M3-03 ■SY-M3-04 ■SY-AN-05 ■SY-OP-06 *For more details, please refer to the PDF document or feel free to contact us.

  • Other electronic parts
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IP Core 'IP_SMPTE2022_Video'

IP Core 'IP_SMPTE2022_Video'

An IP core that addresses network packet loss and ordering!

The "IP_SMPTE2022_Video" is an IP core compliant with SMPTE2022-5/6/7. It can handle multiple port inputs or outputs of 20-bit parallel data for 3G/HD. Additionally, changes on the line side are possible. It can support 10GbE/25GbE/40GbE (10GbE×4)/100GbE (25GbE×4), among others. 【Features】 ■ Error correction function using FEC compliant with SMPTE2022-5-2007 ■ MAC/IP/UDP/RTP filtering ■ Support for both IPv4 and IPv6 ■ Capability to include ARP ■ Hitless support compliant with SMPTE2022-7 (Hitless compatible) *For more details, please download the PDF or feel free to contact us.

  • Software (middle, driver, security, etc.)
  • Other embedded systems (software and hardware)
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CoaXpress(R) camera-side IP core

CoaXpress(R) camera-side IP core

By simply writing image data, high-speed transmission of video can be achieved!

Our "CoaXpress(R) Camera-side IP Core" is an IP core compliant with the industrial camera interface CoaXpress V1.1. This product uses coaxial cables, achieving a performance of 25Gbps (effective 20Gbps) by utilizing up to four cables, each capable of 6.25Gbps (effective 5Gbps). The cables can be extended up to several tens to 100 meters, allowing for the placement of the camera further away from the PC used for video capture, thereby increasing the flexibility of equipment installation. 【Features】 - Supports stream packet transmission, control packet transmission/reception, and trigger reception functions. - Transmission is possible without a frame buffer due to the idle word insertion function. - The use of a high-speed serializer within the FPGA allows for miniaturization of the device. - Minimal footprint (approximately 1000 slices per lane on Kintex-7). - Link speeds can be dynamically changed from 1.25Gbps to 6.25Gbps. - Supports from 1 lane (effective 5Gbps) to 4 lanes (effective 20Gbps). *For more details, please download the PDF or feel free to contact us.

  • Embedded system design service
  • Other cable related products
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GigE Vision IP Core

GigE Vision IP Core

A hardware/firmware library for PTP is available, allowing PTP functionality to be implemented with inexpensive FPGAs and Ethernet PHYs.

This product is an IP core compliant with the industrial camera interface GigE Vision V2.0. It hardware-accelerates the image transmission function that requires high-speed transfer, while other slower processing is handled by the firmware of the FPGA's internal processor. Additionally, the firmware library is provided in C source code, allowing for modifications and additions of functions as needed. Furthermore, it supports PTP/IEEE1588 adopted in GigE Vision 2.0. This feature does not require any special external Ethernet PHY or MAC. 【Features】 ■ GVSP function: In addition to essential core functions, it supports Chunk Data ■ Supports PTP/IEEE1588 ■ Firmware supports not only slave but also simple master functionality ■ Comes with a reference design that operates as a GigE Vision camera ■ Measures PTP error while performing image transfer at 4000x3000x9.5fps *For more details, please refer to the PDF document or feel free to contact us.

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USB3 Vision Library

USB3 Vision Library

It operates solely with firmware without consuming FPGA fabric.

This product is a firmware library compliant with the industrial camera interface USB3 Vision V1.01. It operates on the Xilinx FPGA ZYNQ Ultrascale+ and uses the built-in USB3.0 hard core block, allowing it to function solely with firmware without consuming FPGA fabric. Additionally, it can quickly transfer results from stereo cameras or AI-based image recognition processing to a PC without incurring additional FPGA costs or requiring external devices for USB3.0. 【Features】 ■ Compliant with the industrial camera interface USB3 Vision V1.01 ■ Cortex-R5 can be used as the processor to run the firmware ■ Does not consume resources from Cortex-A53 needed for image processing ■ Capable of sending multiple components with different formats of image data simultaneously ■ Supports Chunk Data *For more details, please refer to the PDF document or feel free to contact us.

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ZIA ISP Optimal Small IP for AI Camera System

ZIA ISP Optimal Small IP for AI Camera System

This is an IP product that realizes high image quality and high performance for AI camera systems.

Compatible with Sony's IMX390 image sensor HDR functionality, it can support high-sensitivity cameras with low noise and a wide dynamic range even in harsh environments such as rain, fog, and backlighting. It can be utilized in products that require high visibility, such as mobility, safety support systems, and surveillance systems. Product introduction manufacturer website: https://www.dmprof.com/ja/products-and-services/ai-products/hardware/ip-core/zia-isp.html

  • Other semiconductors
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IP core "AndesCore A25"

IP core "AndesCore A25"

It also includes modes for low power consumption and power management, as well as a debugging interface!

The "AndesCore A25" is a 32-bit CPU IP core based on the AndeStar V5 architecture, which incorporates RISC-V technology. It achieves high performance per MHz and operates at high frequencies with a low gate count. Additionally, the Andes Custom Extension (ACE) is offered as an option to add custom instructions that lead to performance improvements and optimization of performance/power. 【Specifications (partial)】 ■ AndeStar V5 Instruction Set Architecture (ISA) utilizing RISC-V technology ■ DSP/SIMD ISA suitable for digital signal processing ■ Floating-point extension ■ Andes extension features that enable high performance and high functionality *For more details, please refer to the related links or feel free to contact us.

  • ASIC
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IP core "AndesCore D25F"

IP core "AndesCore D25F"

A flexibly configurable platform to support a wide range of system event scenarios!

The "AndesCore D25F" is a 32-bit CPU IP core based on the AndeStar V5 architecture, which incorporates RISC-V technology. For Linux-based applications, it supports the RISC-V P-extension (draft) DSP/SIMD ISA, which has been significantly contributed to by Andes Technology, as well as single-precision/double-precision floating-point instructions and an MMU. Additionally, options are available for branch prediction for efficient branch instruction execution, instruction and data caches, local memory for low-latency access, and ECC for L1 memory soft error protection. 【Specifications (partial)】 ■ AndeStar V5 Instruction Set Architecture (ISA) utilizing RISC-V technology ■ DSP/SIMD ISA suitable for digital signal processing ■ Floating-point extension ■ Andes extensions that enable high performance and high functionality *For more details, please refer to the related links or feel free to contact us.

  • ASIC
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IP core "AndesCore A25MP"

IP core "AndesCore A25MP"

Symmetric multi-processor with up to 4 cores! Supports level-2 cache and cache coherence.

The "AndesCore A25MP" is a 32-bit multi-core CPU IP core based on the AndeStar V5 architecture. It features an MMU for Linux-based applications, branch prediction for efficient branch instruction execution, level-1 instruction and data caches, and local memory for low-latency access. Additionally, it supports up to four cores and a level-2 cache controller with instruction and data prefetch. 【Specifications (partial)】 ■ Symmetric multiprocessor with up to 4 cores ■ Supports level-2 cache and cache coherence ■ AndeStar V5 Instruction Set Architecture (ISA) Compliant with RISC-V ISA IMACFDN, including Andes performance/function extensions ■ Floating-point extension *For more details, please refer to the related links or feel free to contact us.

  • ASIC
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IP core "AndesCore N9"

IP core "AndesCore N9"

Designers can set specific parameters to adjust the size, power consumption, and performance of the CPU!

The "AndesCore N9" is an IP core designed for applications that require interrupt response capabilities, such as wireless networking, sensors, microcontrollers, and automotive electronics. The low-power N9 family processor has a small gate count, low interrupt latency, and low-cost debugging. The processor family provides excellent performance and outstanding interrupt handling response while addressing the challenges of low dynamic and static power constraints. 【Specifications】 ■ High-performance V3 ISA based on a compact CPU architecture ■ Excellent overall performance ■ Efficient pipeline optimized for local memory access ■ High configurability including AXI bus support *For more details, please refer to the related links or feel free to contact us.

  • ASIC
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IP core "AndesCore N13"

IP core "AndesCore N13"

With an 8-stage pipeline and a clock frequency exceeding 1GHz, the core delivers excellent performance of 2.05 DMIPS/MHz!

The "AndesCore N13" is a high-performance CPU core designed for compute-intensive applications running on operating systems or bare metal. It is designed to meet the stringent requirements of application processors for consumer electronics such as HDTVs, home media servers, and set-top boxes, as well as the SoCs for switches and routers that deliver content to these devices. Equipped with a memory management unit, L1/L2 cache, local memory, DMA, FPU, vector interrupts, and branch prediction, it can easily run complex operating systems like Linux. 【Specifications】 ■ Optimized pipeline for best performance at 1GHz or higher ■ Dynamic branch prediction accelerates loop execution ■ ULM (Unified Local Memory) for parallel access ■ 64-bit AXI bus for high bandwidth and low latency ■ MMU and MPU for Linux and RTOS ■ Supports FPU coprocessor and L2 cache *For more details, please refer to the related links or feel free to contact us.

  • ASIC
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IP core "AndesCore N10"

IP core "AndesCore N10"

You can bridge the internet connection of ZigBee, Bluetooth, or WiFi sensor devices!

The "AndesCore N10" is an IP core suitable for applications ranging from consumer media players and smart glasses to touch panels, motor control, and power management. It features a 5-stage pipeline and operates at clock frequencies exceeding 800MHz, providing sufficient performance for automotive electronics and industrial control. Additionally, it comes with I/D cache or local memory options, allowing the core to run more efficiently in network or communication applications. 【Specifications】 ■ Cache for high-speed code and data access ■ Local memory for code and data access ■ IEEE754 compliant FPU coprocessor ■ Memory Protection Unit (MPU) for secure RTOS ■ Memory Management Unit (MMU) for Linux *For more details, please refer to the related links or feel free to contact us.

  • ASIC
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IP core "AndesCore E8"

IP core "AndesCore E8"

FlashFetch improves performance while saving power!

The "AndesCore E8" is a power-efficient and compact embedded controller enabled by the unique Andes Custom Extension (ACE). With its proprietary ACE environment, designers can specify architectural elements suitable for IoT applications. Using Andes' Custom-Optimized Instruction Development Tools (COPILOT), designers can create custom instructions that differentiate their products and designs from competing products based on standard instruction set processors. 【Specifications】 ■ Class-leading performance per MHz ■ Andes Custom Extension (ACE) significantly improves performance efficiency ■ Small footprint with fewer gates and high code density ■ Faster flash access and reduced power consumption through FlashFetch technology *For more details, please refer to the related links or feel free to contact us.

  • ASIC
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SAS Target IP Core for FPGA and ASIC

SAS Target IP Core for FPGA and ASIC

Supports SAS 3.0Gbps, 6.0Gbps, and 12.0Gbps! Equipped with automatic credit control function.

The "IP Core SAS Target for FPGA and ASIC" complies with the SAS 3.0 standard and supports a maximum transfer rate of 12Gbps (1200MB/s) for Serial-SCSI (SAS) target (device). It consists of four blocks (Phy layer, LINK layer, PORT layer, TRN layer) and interfaces with processors, SerDes, and memory. It is designed to connect to SAS-compliant host applications to transmit and receive OOB signals, primitives, and SAS frames. 【Specifications (Excerpt)】 ■ Compliant with SAS 3.0 standard ■ Supports SAS 3.0Gbps, 6.0Gbps, and 12.0Gbps ■ Register access to link layer/transport layer ■ Supports SerDes, PIPE, and SAPIS interfaces ■ Supports OOB sequence and speed negotiation sequence *For more details, please download the PDF or feel free to contact us.

  • ASIC
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Quantum-resistant cryptographic IP core for financial institutions

Quantum-resistant cryptographic IP core for financial institutions

Protecting financial transactions from the threat of quantum computers.

In the financial industry, advanced security measures are essential to protect customers' assets and confidential information. Particularly with the advent of quantum computers, the risk of traditional encryption technologies being compromised has increased. To safeguard transactions from this threat, the implementation of post-quantum cryptography is urgent. Our "Post-Quantum Cryptography IP Core" provides a hardware-level security solution that uses algorithms selected by NIST and CNSA to protect data and hardware from quantum computer attacks. 【Use Cases】 * Online banking * Credit card payments * Securities trading * Data communication between financial institutions 【Benefits of Implementation】 * Enhanced safety of customer data * Increased reliability of financial transactions * Compliance with regulations * Assurance of business continuity

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[For Government] Quantum-resistant Cryptographic IP Core

[For Government] Quantum-resistant Cryptographic IP Core

Security solutions that protect data and hardware.

In government agencies, advanced security measures are essential to protect national secrets and important information assets of the citizens. The development of quantum computers poses a threat to traditional encryption technologies, increasing the risk of information leakage. Therefore, solutions that can protect data from attacks by quantum computers and ensure security are in demand. 【Use Cases】 * Protection of confidential data in government agencies * Strengthening the security of critical infrastructure * Ensuring the confidentiality of communications 【Benefits of Implementation】 * Reduction of risks associated with decryption by quantum computers * Prevention of national losses due to information leakage * Establishment of a secure information communication environment

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Quantum-resistant cryptographic IP core for healthcare

Quantum-resistant cryptographic IP core for healthcare

Hardware-level security that protects the safety of medical data.

In the healthcare industry, protecting patients' confidential information and medical data is the top priority. The advancement of quantum computers threatens traditional encryption technologies, increasing the risk of unauthorized access and data breaches for these critical data. To protect patient privacy and maintain the reliability of healthcare institutions, the implementation of quantum-resistant encryption technology is essential. 【Use Cases】 * Electronic medical record systems * Telemedicine platforms * Data management in research institutions * Communication of medical devices 【Benefits of Implementation】 * Protection of data from attacks by quantum computers * Maintenance of patient data confidentiality * Strengthening the security of medical information systems * Compliance with regulations

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