We have compiled a list of manufacturers, distributors, product information, reference prices, and rankings for IP Cores.
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IP Cores Product List and Ranking from 29 Manufacturers, Suppliers and Companies

Last Updated： Aggregation Period:Sep 17, 2025～Oct 14, 2025
This ranking is based on the number of page views on our site.

IP Cores Manufacturer, Suppliers and Company Rankings

Last Updated： Aggregation Period:Sep 17, 2025～Oct 14, 2025
This ranking is based on the number of page views on our site.

  1. 富士ソフト インダストリービジネス事業部 Kanagawa//software
  2. デザイン・ゲートウェイ Tokyo//Electronic Components and Semiconductors
  3. Euresys Japan ユレシス　ジャパン Kanagawa//Electronic Components and Semiconductors
  4. 4 NSCore Fukuoka//Electronic Components and Semiconductors
  5. 5 サイレックス・テクノロジー Kyoto//Other manufacturing
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IP Cores Product ranking

Last Updated： Aggregation Period:Sep 17, 2025～Oct 14, 2025
This ranking is based on the number of page views on our site.

  1. Wireless LAN Survey "WM-100" サイレックス・テクノロジー
  2. A system to notify when passing by to prevent forklift accidents in the factory. パシフィック湘南
  3. MTP non-volatile memory IP core 'TwinBit' NSCore
  4. NVMe IP core for FPGA デザイン・ゲートウェイ
  5. 4 IP cores for FPGA and ASIC manufactured by System-On-Chip. 富士ソフト インダストリービジネス事業部

IP Cores Product List

46～60 item / All 101 items

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TOE10G-IP core for FPGA

TOE10G-IP core for FPGA

Achieving 10 times faster 10GbE TCP/IP communication functionality with pure hardware logic without CPU!

The 10GbE TCP Offloading Engine IP Core (TOE10G-IP) is a groundbreaking solution that allows complex TCP transmission and reception processing, which traditionally required expensive high-end CPUs, to be implemented solely with pure hardware logic without a CPU. It comes standard with a reference design compatible with Xilinx/Intel FPGAs, which can help shorten product development time.

  • ASIC

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USB 3.0 IP core for FPGA

USB 3.0 IP core for FPGA

With the USB3.0 IP core, it is possible to develop a highly versatile FAT32 data recorder in a short period of time!

The 【USB3.0-IP】 complies with the USB3.0 standard Revision 1.0 and includes both the link layer and protocol layer, making it easy to implement a USB3.0 interface when combined with an external PHY chip from TI. A reference design compatible with Xilinx/Altera FPGAs is included as standard with the core product, which can help shorten product development time.

  • ASIC

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TOE40G-IP core for FPGA

TOE40G-IP core for FPGA

Achieving 40 times speed 10GbE TCP/IP communication functionality with pure hardware logic without CPU!

The 40GbE TCP Offloading Engine IP Core (TOE40G-IP) is a groundbreaking solution that enables the complex TCP transmission and reception processes, which traditionally required expensive high-end CPUs, to be implemented solely with pure hardware logic without a CPU. It comes standard with a reference design compatible with Xilinx/Intel FPGAs, which can help shorten product development time.

  • ASIC

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UHF Band RFID Reader/Writer Module【TPURID2100】

UHF Band RFID Reader/Writer Module【TPURID2100】

Space-saving design of 41×32×5.3mm. Control of 920MHz band RFID with MicroPython expands the possibilities of embedded devices.

- High-performance module equipped with the latest chip from Impij - Compact and energy-efficient, making it easy to embed - Capable of standalone operation with MicroPython - Easily combinable with sensors and communication modules - Ideal for inventory management and history management, and can be utilized in a wide range of scenes such as apparel, logistics, and distribution.

  • Communications
  • Other electronic parts
  • RFID related products and IC tag services

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2.4GHz band wireless module [TPBPM]

2.4GHz band wireless module [TPBPM]

Accelerate IoT development with MicroPython! A compact 2.4GHz wireless module that achieves low power consumption with LPWA compatibility.

TPBPM is a compact, lightweight, and low power consumption 2.4GHz wireless module. It supports a unique (FSK modulation) mode and BLE. It is equipped with MicroPython, allowing sensors to be directly attached and operate independently. We offer a starter kit that makes it easy to verify the module's operation.

  • Other electronic parts
  • Communications
  • Embedded system design service

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CoaXPress IP Core

CoaXPress IP Core

It is designed to be compact so that the necessary space for the application can be secured on the FPGA.

We would like to introduce the 'CoaXPress IP Core' that we handle. The CoaXPress interface provides a series of IP cores and development frameworks for building FPGA-based transmitters. Additionally, the CXP core is compatible with AMD 7 series (and later), Intel Cyclone V devices (and later), and Microchip PolarFire series. 【Features】 ■ Minimizes development time ■ Achieves top-class performance with a minimal footprint ■ Ensures sufficient flexibility to customize designs ■ Receives all data output from video sensors to CXP PHY ■ Implements control channels according to CXP specifications *For more details, please download the PDF or feel free to contact us.

  • Other embedded systems (software and hardware)

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USB3 Vision IP Core

USB3 Vision IP Core

For engineers aiming for product development in the short to medium term! Compact and customizable.

We would like to introduce our "USB3 Vision IP Core." We provide a set of IP cores and development frameworks for building FPGA-based products using the USB3 Vision interface. It is also compatible with AMD 7 series devices (and later) and Intel Cyclone V devices (and later). 【Features】 ■ Minimizes development time while achieving top-class performance with a small footprint ■ Ensures sufficient flexibility to customize designs ■ Option to have the source code of the embedded USB3 Vision library running on the Cypress FX3 USB controller *For more details, please download the PDF or feel free to contact us.

  • Other embedded systems (software and hardware)

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MIPI CSI-2 Receiver IP Core

MIPI CSI-2 Receiver IP Core

Helps connect MIPI sensors from various vendors to FPGA!

We offer the 'MIPI CSI-2 Receiver IP Core', which allows for easy camera design. It is provided as encrypted VHDL, and the VHDL source code is available as an option. Additionally, the MIPI CSI-2 receiver IP software library is provided as an object file, with the option to obtain it as C source code. 【Features】 ■ Compatible with AMD Artix7, Kintex7, Zynq7, and Ultrascale+ FPGAs ■ Comes with a complete reference design for S2I's MVDK equipped with Zynq7 or Ultrascale+ FPGA and IMX MIPI FMC module ■ Easy to port designs to other FPGA platforms *For more details, please download the PDF or feel free to contact us.

  • Other embedded systems (software and hardware)

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IntelliProp's IP cores for FPGA and ASIC.

IntelliProp's IP cores for FPGA and ASIC.

Providing high-quality and high-performance IP core products for the storage industry! Supporting the development of ASSP products as well.

IntelliProp develops high-quality and high-performance IP core products and ASSP products for the storage industry. Since its establishment in 1998, the company has been providing competitive IP core products as a leading company in specialized fields such as SATA, SAS, PCIe/NVMe, NAND flash, security/encryption, and RAID technology in Longmont, Colorado, USA, where major companies in the storage industry gather. *For more details, please refer to the PDF document or feel free to contact us.*

  • Embedded Board Computers
  • Other network tools
  • Other embedded systems (software and hardware)

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IP cores for FPGA and ASIC manufactured by System-On-Chip.

IP cores for FPGA and ASIC manufactured by System-On-Chip.

High quality, low latency, power-saving IP Core

Providing a group of MPEG standard codecs as IP Cores with high quality, low latency, low power consumption, and a small footprint. Available in Intel FPGA and Xilinx versions.

  • Embedded Board Computers
  • Other network tools
  • Other embedded systems (software and hardware)

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IP core "AndesCore AX25"

IP core "AndesCore AX25"

64-bit CPU architecture! It can access an address space significantly exceeding 4GB.

The "AndesCore AX25" is a compact 64-bit CPU IP core based on the AndeStar V5 architecture, which incorporates RISC-V technology. It is optimized for high-performance embedded applications that require access to an address space exceeding 4GB. Options such as branch prediction for efficient branch instruction execution, instruction and data caches, local memory for low-latency access, and ECC for L1 memory soft error protection are available. 【Specifications (partial)】 ■ AndeStar V5 Instruction Set Architecture (ISA) utilizing RISC-V technology ■ DSP/SIMD ISA suitable for digital signal processing ■ Floating-point extension ■ Andes extensions that enable high performance and high functionality *For more details, please refer to the related links or feel free to contact us.

  • ASIC

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SATA Host APP for FPGA and ASIC IP Cores

SATA Host APP for FPGA and ASIC IP Cores

Equipped with a self-test! Supports power modes (partial/slumber).

We would like to introduce our "SATA Host APP IP Core for FPGA and ASIC." This is an IP core for SATA hosts that complies with the SATA 3.3 standard and supports a maximum transfer rate of 6Gbps (600MB/s). It consists of the PHY layer, LNK layer, TRN (Transport) layer, application layer, SerDes, and FIFO interface. 【Specifications】 ■ Complies with SATA Revision 3.3 standard (1.5Gbps, 3.0Gbps, 6.0Gbps) ■ Supports OOB (Out of Band) ■ Uses FIFO for the DATA interface ■ Supports either SerDes, PIPE, or SAPIS interfaces ■ Supports power modes (partial/slumber) ■ Equipped with self-test functionality *For more details, please download the PDF or feel free to contact us.

  • ASIC

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SATA Host AHCI IP Core for FPGA/ASIC

SATA Host AHCI IP Core for FPGA/ASIC

It can widely support systems that require a SATA host!

The "IP Core SATA Host AHCI for FPGA/ASIC" complies with the SATA 3.3 standard and supports a maximum transfer rate of 6Gbps (600MB/s) for SATA hosts. With the AHCI interface, it can be easily connected using standard drivers. Additionally, it consists of the SATA core [Phy layer, LNK layer, TRN (Transport) layer], SATA host application, and AHCI layer. 【Specifications (Excerpt)】 ■ Complies with SATA Revision 3.3 standard (1.5Gbps, 3.0Gbps, 6.0Gbps) ■ Supports OOB (Out of Band) ■ Supports either SerDes, PIPE, or SAPIS interfaces ■ Supports power modes (partial/slumber) ■ Equipped with self-test functionality *For more details, please download the PDF or feel free to contact us.

  • ASIC

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SAS Initiator IP Core for FPGA/ASIC

SAS Initiator IP Core for FPGA/ASIC

OOB sequence and speed negotiation sequence support!

The "IP Core SAS Initiator for FPGA/ASIC" complies with the SAS 3.0 standard and supports a maximum transfer rate of 12Gbps (1200MB/s) for Serial-SCSI (SAS) initiators (hosts). It consists of four blocks (Phy layer, LINK layer, PORT layer, TRN layer), along with a processor, SerDes, and memory interface. It is designed to connect to SAS-compliant device applications to transmit and receive OOB signals, primitives, and SAS frames. 【Specifications (Excerpt)】 ■ Compliant with SAS 3.0 standard ■ Supports SAS 3.0Gbps, 6.0Gbps, and 12.0Gbps ■ Register access to link layer/transport layer ■ Supports SerDes, PIPE, and SAPIS interfaces ■ Supports OOB sequence and speed negotiation sequence *For more details, please download the PDF or feel free to contact us.

  • ASIC

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IP core for FPGA/ASIC NVMe Target

IP core for FPGA/ASIC NVMe Target

Register access from the processor is available! Command interrupt support is included.

We would like to introduce the 'FPGA/ASIC IP Core for NVMe Target' handled by Fujisoft Inc. It is equipped with NVMe command queuing response functionality, allowing it to be used in high-performance storage products that take advantage of NVMe's high data transfer speeds. This is an IP core for NVMe targets that complies with the NVMe 1.4 specification and operates on PCIe 4.0 (8Gbps) x 8 lanes. 【Specifications (Excerpt)】 ■ Compliant with NVM Express 1.4 specification ■ Compatible with third-party PCIe Root Complex IP cores ■ Application layer with an interface to the processor ■ FIFO data interface ■ Register access from the processor is possible *For more details, please download the PDF or feel free to contact us.

  • ASIC

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