We have compiled a list of manufacturers, distributors, product information, reference prices, and rankings for IP Cores.
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IP Cores Product List and Ranking from 14 Manufacturers, Suppliers and Companies

Last Updated： Aggregation Period:Jul 23, 2025～Aug 19, 2025
This ranking is based on the number of page views on our site.

IP Cores Manufacturer, Suppliers and Company Rankings

Last Updated： Aggregation Period:Jul 23, 2025～Aug 19, 2025
This ranking is based on the number of page views on our site.

  1. デザイン・ゲートウェイ Tokyo//Electronic Components and Semiconductors
  2. NSCore Fukuoka//Electronic Components and Semiconductors
  3. Panasonic Holdings Corporation / Nessum Department Fukuoka//IT/Telecommunications
  4. 富士ソフト Kanagawa//software インダストリービジネス事業部
  5. 5 メティエ Niigata//Consumer Electronics
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IP Cores Product ranking

Last Updated： Aggregation Period:Jul 23, 2025～Aug 19, 2025
This ranking is based on the number of page views on our site.

  1. Nessum (formerly HD-PLC) IP core Panasonic Holdings Corporation / Nessum Department
  2. MTP non-volatile memory IP core 'TwinBit' NSCore
  3. OTP Non-volatile Memory IP Core 'PermSRAM' NSCore
  4. 4 SATA IP core for FPGA デザイン・ゲートウェイ
  5. 4 USB 3.0 IP core for FPGA デザイン・ゲートウェイ

IP Cores Product List

16～30 item / All 81 items

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25G TOE IP core for FPGA

25G TOE IP core for FPGA

Achieving 25G TCP/IP communication functionality with pure hardware logic without CPU!

The 25GbE TCP Offloading Engine IP Core (TOE25G-IP) is a groundbreaking solution that enables the complex TCP transmission and reception processes, which traditionally required expensive high-end CPUs, to be implemented solely with pure hardware logic without a CPU. It comes standard with a reference design compatible with Xilinx/Intel FPGAs, which can help shorten product development time. It provides 25G performance and bandwidth, which is 2.5 times that of the conventional 10G in a single channel. This significantly reduces power consumption and cost per gigabit.

  • ASIC

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TOE100G-IP core for FPGA

TOE100G-IP core for FPGA

Achieving 100G TCP/IP communication functionality with pure hardware logic without CPU!

The 100GbE TCP Offloading Engine IP Core (TOE100G-IP) is a groundbreaking solution that enables the implementation of complex TCP transmission and reception processes, which traditionally required expensive high-end CPUs, using only pure hardware logic without a CPU. It comes standard with a reference design compatible with Xilinx/Intel FPGAs, which can help shorten product development time.

  • ASIC

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LDPC IP core

LDPC IP core

We provide a total solution for LDPC codes, from system design and computer simulation evaluation to IP macros.

LDPC (Low Density Parity Check) symbols LDPC symbols have error correction capabilities that are extremely close to the Shannon limit, and they are error correction codes that enable high-speed processing of codes through parallel processing. Features of Mobile Tech's LDPC Symbol Total Solution We provide Encoder/Decoder IPs with optimal configurations based on the required performance (circuit scale/througput) that support standard LDPC codes as well as customer-specific LDPC codes, and we also design and support peripheral modules to maximize performance.

  • Other network tools

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Northwest Logic's IP cores for FPGA and ASIC.

Northwest Logic's IP cores for FPGA and ASIC.

Achieving high performance and high quality of standalone controller IP cores, in collaboration with PHY IP vendors and verification IP vendors!

Northwest Logic has been providing controller IP cores focused on memory interfaces, MIPI, and PCI Express since its establishment in 1995. For memory interfaces, we offer a wide range of controllers including HBM2, DDR4/3, and LPDDR4, as well as CSI-2 and DSI-2/DSI for MIPI, and Gen4/3 for PCI Express. Our customizable IP cores are equipped with the full functionality of each protocol and are compatible with both ASIC and FPGA platforms. In addition to achieving high performance and quality for standalone controller IP cores through extensive simulation and hardware verification, we also focus on collaboration with PHY IP vendors and verification IP vendors, enabling us to provide total solutions for customers looking to integrate memory interfaces, MIPI, and PCI Express functionalities into their systems. *For more details, please refer to the PDF materials or feel free to contact us.

  • Other network tools
  • Other embedded systems (software and hardware)

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FPGA-compatible MECHATROLINK communication IP 'SYM3A'

FPGA-compatible MECHATROLINK communication IP 'SYM3A'

Mechatrolink communication macros can be implemented on intel-FPGA.

This is a soft IP that enables the implementation of the MECHATOROLINK-III communication protocol on FPGA. It flexibly accommodates the addition of various interfaces and peripheral circuits, which are features of FPGAs, and allows for easy design integration using the GUI of the Qsys system integration tool. The basic functionality of this IP is equivalent to Yaskawa Electric's JL-100/JL-102. It is easy to build an evaluation environment by combining the Macnica Sodia board with our SY-M3-03 board. High functionality and high-speed processing are achieved through cooperative operation between the ARM Cortex-A9 and user circuits (ARM is used when employing Intel FPGA SoC). * Operation has been confirmed on the Macnica Sodia-Cyclone V ST SoC evaluation board. ■ Supports C1 master/slave/multi-slave configurations ■ Netlist provided as a Soft-IP core ■ MECHATROLINK-III certification obtained

  • Other semiconductors

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High-speed reversible data compression IP core for FPGA 'CVC Codec'

High-speed reversible data compression IP core for FPGA 'CVC Codec'

To streamline system research and development! Efficiently compress measurement data to contribute to the development of autonomous driving technology.

The "CVC Codec" is an IP library that implements our original lossless data compression algorithm, CVC method, specialized for natural information such as image data and waveform data on FPGA. It features a compact circuit size, making it easy to implement into existing systems. The processing speed is stable, providing excellent real-time performance. Additionally, it boasts a higher compression ratio compared to conventional lossless compression. 【Features】 ■ Efficiently compresses measurement data, contributing to the development of autonomous driving technology ■ Achieves overwhelming high-speed processing ■ Compression starts instantly after data input, with low latency design ■ Stable processing speed, excelling in real-time performance ■ Easy implementation into existing systems with a compact circuit size *For more details, please refer to the PDF materials or feel free to contact us.

  • others

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IP Core 'IP_SMPTE2059_SLV'

IP Core 'IP_SMPTE2059_SLV'

Compliant with SMPTE 2059-1/2! Hitless time synchronization is possible through line redundancy.

The "IP_SMPTE2059_SLV" is an IP core for slaves compliant with ST 2059-1/2. There are two types: the vPTPM (Master-Core) on the master side and the vPTPS (Slave-Core) on the slave side, which can be used individually, in multiples, or in combination. Additionally, it has ports for sending and receiving control packets from the MPU bus and is compatible with NMOS, among others. 【Features】 ■ Compliant with SMPTE 2059-1/2 ■ Counter output for PTS ■ 1PPS output ■ Serial output of time information ■ Capable of sending and receiving control packets using the MPU *For more details, please refer to the PDF documentation or feel free to contact us.

  • others

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IP Core "IP_SMPTE2110"

IP Core "IP_SMPTE2110"

The video format supports 4K/HD/SD! You can manage Ethernet statistics.

The "IP_SMPTE2110" is an IP core compliant with ST 2110-10/20/30/40. It comes in two types: vEGSV (Egress-Core) for the transmission side and vIGSV (Ingress-Core) for the reception side. They can be used individually, in multiples, or in combination. Additionally, the number of SDI channels and Ethernet ports can be freely combined. 【Features】 ■ Compliant with SMPTE 2110-10/20/30 ■ Supports video formats 4K/HD/SD ■ SMPTE 2022-7 (Hitless support) ■ Capable of supporting control in-channel communication ■ Compatible with IPv4 and IPv6 *For more details, please refer to the PDF document or feel free to contact us.

  • others

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Nessum (formerly HD-PLC) IP core

Nessum (formerly HD-PLC) IP core

Semiconductor IP core that enables communication over any media, such as wired, wireless, and underwater! It is an international standard technology that achieves high-speed, long-distance, and reduced wiring.

The "Nessum IP Core" is a semiconductor IP core compliant with the international standard IEEE 1901c, enabling both wired communication using existing metal lines (control lines, coaxial lines, power lines, etc.) and short-range wireless communication. Based on a standard mode with a maximum physical speed of 250 Mbps, it allows for narrowing the frequency band up to 32 divisions or widening it up to four times, making long-distance and high-speed communication possible. 【Features】 ■ Enables long-distance, high-speed, and reduces wiring communication ■ Supports wide-area networking with up to 1024 nodes ■ Complies with international standards such as IEEE and ITU-T ■ Allows for resource-saving through functional selection tailored to applications ■ Provides an environment for compatibility certification and performance evaluation at the Nessum test site For more details, please refer to the PDF document or feel free to contact us.

  • LAN construction and wiring work

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Dynamic Neural Accelerator(DNA)

Dynamic Neural Accelerator(DNA)

Seamlessly accelerate increasingly complex compute-intensive AI workloads!

The "Dynamic Neural Accelerator (DNA)" is a flexible deep learning inference IP core characterized by high computational power, ultra-low latency, and a scalable inference engine. While boasting excellent power efficiency compared to other standard processors, it achieves ultra-low latency for inference in streaming data. Please feel free to contact us if you have any inquiries. 【Features】 ■ Ultra-low latency AI inference IP core ■ Robust open-source MERA software framework ■ Compatible with both FPGA and ASIC/SoC (The photo and link below show an example of DNA mounted on the Bittware (Molex Japan) FPGA card IA420F.) *For more details, please refer to the link below, download the PDF, or contact us. Reference link: https://www.bittware.com/ja/ip-solutions/edgecortix-dynamic-neural-accelerator/

  • others

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OTP Non-volatile Memory IP Core 'PermSRAM'

OTP Non-volatile Memory IP Core 'PermSRAM'

Achieving affordable and reliable shipping inspections! We support high quality and stable yields.

"PermSRAM" is an OTP non-volatile memory IP core that can be manufactured using standard logic processes. It provides non-volatile memory that can be written only once for a wide range of processes, from the 0.18um generation to advanced 28nm generations and beyond. Customization is possible for various non-volatile memory core applications, ranging from 64b latch types to 1MByte code storage memory. 【Features】 ■ World-class smallest area ■ Reverse engineering resistance ■ Low voltage writing ■ Equipped with test circuits ■ Automotive grade (guaranteed up to 150℃) *For more details, please refer to the PDF document or feel free to contact us.

  • Memory
  • Other electronic parts

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