We have compiled a list of manufacturers, distributors, product information, reference prices, and rankings for IP Cores.
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IP Cores Product List and Ranking from 29 Manufacturers, Suppliers and Companies | IPROS GMS

Last Updated： Aggregation Period:Feb 04, 2026～Mar 03, 2026
This ranking is based on the number of page views on our site.

IP Cores Manufacturer, Suppliers and Company Rankings

Last Updated： Aggregation Period:Feb 04, 2026～Mar 03, 2026
This ranking is based on the number of page views on our site.

  1. 富士ソフト インダストリービジネス事業部 Kanagawa//software
  2. デザイン・ゲートウェイ Tokyo//Electronic Components and Semiconductors
  3. Euresys Japan ユレシス　ジャパン Kanagawa//Electronic Components and Semiconductors
  4. 4 サイレックス・テクノロジー Kyoto//Other manufacturing
  5. 5 ネットワークアディションズ Kanagawa//IT/Telecommunications
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IP Cores Product ranking

Last Updated： Aggregation Period:Feb 04, 2026～Mar 03, 2026
This ranking is based on the number of page views on our site.

  1. Wireless LAN Survey "WM-100" サイレックス・テクノロジー
  2. TOE10G-IP core for FPGA デザイン・ゲートウェイ
  3. A system to notify when passing by to prevent forklift accidents in the factory. パシフィック湘南
  4. 4 IP core for FPGA/ASIC NVMe Target 富士ソフト インダストリービジネス事業部
  5. 5 JPEG compression IP core (Verilog) メティエ

IP Cores Product List

31～60 item / All 117 items

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FPGA-compatible MECHATROLINK communication IP 'SYM3A'

FPGA-compatible MECHATROLINK communication IP 'SYM3A'

Mechatrolink communication macros can be implemented on intel-FPGA.

This is a soft IP that enables the implementation of the MECHATOROLINK-III communication protocol on FPGA. It flexibly accommodates the addition of various interfaces and peripheral circuits, which are features of FPGAs, and allows for easy design integration using the GUI of the Qsys system integration tool. The basic functionality of this IP is equivalent to Yaskawa Electric's JL-100/JL-102. It is easy to build an evaluation environment by combining the Macnica Sodia board with our SY-M3-03 board. High functionality and high-speed processing are achieved through cooperative operation between the ARM Cortex-A9 and user circuits (ARM is used when employing Intel FPGA SoC). * Operation has been confirmed on the Macnica Sodia-Cyclone V ST SoC evaluation board. ■ Supports C1 master/slave/multi-slave configurations ■ Netlist provided as a Soft-IP core ■ MECHATROLINK-III certification obtained

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High-speed reversible data compression IP core for FPGA 'CVC Codec'

High-speed reversible data compression IP core for FPGA 'CVC Codec'

To streamline system research and development! Efficiently compress measurement data to contribute to the development of autonomous driving technology.

The "CVC Codec" is an IP library that implements our original lossless data compression algorithm, CVC method, specialized for natural information such as image data and waveform data on FPGA. It features a compact circuit size, making it easy to implement into existing systems. The processing speed is stable, providing excellent real-time performance. Additionally, it boasts a higher compression ratio compared to conventional lossless compression. 【Features】 ■ Efficiently compresses measurement data, contributing to the development of autonomous driving technology ■ Achieves overwhelming high-speed processing ■ Compression starts instantly after data input, with low latency design ■ Stable processing speed, excelling in real-time performance ■ Easy implementation into existing systems with a compact circuit size *For more details, please refer to the PDF materials or feel free to contact us.

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IP Core 'IP_SMPTE2059_SLV'

IP Core 'IP_SMPTE2059_SLV'

Compliant with SMPTE 2059-1/2! Hitless time synchronization is possible through line redundancy.

The "IP_SMPTE2059_SLV" is an IP core for slaves compliant with ST 2059-1/2. There are two types: the vPTPM (Master-Core) on the master side and the vPTPS (Slave-Core) on the slave side, which can be used individually, in multiples, or in combination. Additionally, it has ports for sending and receiving control packets from the MPU bus and is compatible with NMOS, among others. 【Features】 ■ Compliant with SMPTE 2059-1/2 ■ Counter output for PTS ■ 1PPS output ■ Serial output of time information ■ Capable of sending and receiving control packets using the MPU *For more details, please refer to the PDF documentation or feel free to contact us.

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IP Core "IP_SMPTE2110"

IP Core "IP_SMPTE2110"

The video format supports 4K/HD/SD! You can manage Ethernet statistics.

The "IP_SMPTE2110" is an IP core compliant with ST 2110-10/20/30/40. It comes in two types: vEGSV (Egress-Core) for the transmission side and vIGSV (Ingress-Core) for the reception side. They can be used individually, in multiples, or in combination. Additionally, the number of SDI channels and Ethernet ports can be freely combined. 【Features】 ■ Compliant with SMPTE 2110-10/20/30 ■ Supports video formats 4K/HD/SD ■ SMPTE 2022-7 (Hitless support) ■ Capable of supporting control in-channel communication ■ Compatible with IPv4 and IPv6 *For more details, please refer to the PDF document or feel free to contact us.

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Nessum (formerly HD-PLC) IP core

Nessum (formerly HD-PLC) IP core

Semiconductor IP core that enables communication over any media, such as wired, wireless, and underwater! It is an international standard technology that achieves high-speed, long-distance, and reduced wiring.

The "Nessum IP Core" is a semiconductor IP core compliant with the international standard IEEE 1901c, enabling both wired communication using existing metal lines (control lines, coaxial lines, power lines, etc.) and short-range wireless communication. Based on a standard mode with a maximum physical speed of 250 Mbps, it allows for narrowing the frequency band up to 32 divisions or widening it up to four times, making long-distance and high-speed communication possible. 【Features】 ■ Enables long-distance, high-speed, and reduces wiring communication ■ Supports wide-area networking with up to 1024 nodes ■ Complies with international standards such as IEEE and ITU-T ■ Allows for resource-saving through functional selection tailored to applications ■ Provides an environment for compatibility certification and performance evaluation at the Nessum test site For more details, please refer to the PDF document or feel free to contact us.

  • LAN construction and wiring work
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Dynamic Neural Accelerator(DNA)

Dynamic Neural Accelerator(DNA)

Seamlessly accelerate increasingly complex compute-intensive AI workloads!

The "Dynamic Neural Accelerator (DNA)" is a flexible deep learning inference IP core characterized by high computational power, ultra-low latency, and a scalable inference engine. While boasting excellent power efficiency compared to other standard processors, it achieves ultra-low latency for inference in streaming data. Please feel free to contact us if you have any inquiries. 【Features】 ■ Ultra-low latency AI inference IP core ■ Robust open-source MERA software framework ■ Compatible with both FPGA and ASIC/SoC (The photo and link below show an example of DNA mounted on the Bittware (Molex Japan) FPGA card IA420F.) *For more details, please refer to the link below, download the PDF, or contact us. Reference link: https://www.bittware.com/ja/ip-solutions/edgecortix-dynamic-neural-accelerator/

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Factory wireless products "Production Visualization System"

Factory wireless products "Production Visualization System"

The future of factories starts with visualizing the workplace.

Arrow Seven is a company that coordinates total network systems centered around wireless communication. We support everything related to wireless communication, from product development to application development. Wireless systems are easily affected by environmental factors on-site, making the accumulation of experience crucial for progressing development and implementation as planned. By specializing in the development of wireless systems, Arrow Seven has gained extensive experience and reflected that technical expertise in our achievements. 【Features】 - Automatic collection of production information via wireless - Graphing with Excel - Easy data transfer in conjunction with production management systems For more details, please contact us or download the catalog.

  • Communications
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DapTechnology FireCore (IP Core)

DapTechnology FireCore (IP Core)

FireCore is an IP core that integrates PHY and link layer controller (LLC) cores into a single IP product.

FireCore integrates the PHY and link layer requirements necessary for common 1394 devices into a single IP core. Based on the FireGate PHY IP core and FireLink LLC IP core, FireCore is designed to support data rates from S100 to S3200 and various host interfaces such as generic, OHCI, and OHCI (with AS5643 option). DapTechnology's new FireCore package offers unprecedented technical capabilities, features, flexibility, and options for customization and future expansion. Together with FireStack (DapTechnology's 1394 software stack), FireCore is designed to fully leverage the capabilities of the AS5643 extension. It aims to completely abstract the 1394 protocol layer and the AS5643 protocol layer, allowing implementers to focus entirely on system-level functionalities such as fault tolerance, fault isolation, and redundancy.

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[Siliconarts] Raytracing GPU IP

[Siliconarts] Raytracing GPU IP

The world's first real-time Ray tracing & Path tracing GPU IP.

A fabless company that owns raytracing GPU IP and is planning to develop artificial intelligence models and AI processors for edge devices as a new business. For chip development, basic logic design is conducted internally, while backend design is primarily carried out through foundry design houses. [RayCore MC] - MIMD-based low-power high-performance real-time raytracing & path tracking GPU - Achieves real-time low-power raytracing functionality.

  • Other semiconductors
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OTP Non-volatile Memory IP Core 'PermSRAM'

OTP Non-volatile Memory IP Core 'PermSRAM'

Achieving affordable and reliable shipping inspections! We support high quality and stable yields.

"PermSRAM" is an OTP non-volatile memory IP core that can be manufactured using standard logic processes. It provides non-volatile memory that can be written only once for a wide range of processes, from the 0.18um generation to advanced 28nm generations and beyond. Customization is possible for various non-volatile memory core applications, ranging from 64b latch types to 1MByte code storage memory. 【Features】 ■ World-class smallest area ■ Reverse engineering resistance ■ Low voltage writing ■ Equipped with test circuits ■ Automotive grade (guaranteed up to 150℃) *For more details, please refer to the PDF document or feel free to contact us.

  • Memory
  • Other electronic parts
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HDMI Specification Receiver IP Core "SLISHDMIR"

HDMI Specification Receiver IP Core "SLISHDMIR"

By connecting with "SLIPHDMIR," it is possible to most efficiently extract performance and characteristics.

SLISHDMIR is an IP core for HDMI receiver link compliant with the HDMI 1.3a standard.

  • Microcomputer
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SD UHS-II PHY IP for SD cards

SD UHS-II PHY IP for SD cards

Achieving a maximum transfer rate of 300MB/s for UHS-II with low power consumption through proprietary technology.

This is a PHY IP solution for the ultra-high-speed interface "UHS-II" that can be used with the new SD card standards SDXC and SDHC.

  • Microcomputer
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IEEE1588-2008 PTP Time Synchronization IP Core

IEEE1588-2008 PTP Time Synchronization IP Core

Providing IEEE1588-2008 PTP time synchronization solutions as an IP core. Synchronizing devices on Ethernet (LAN) with nanosecond precision.

Oregano Systems offers timing synchronization solutions compliant with IEEE1588-2008 Precision Time Protocol as IP CORE. It provides syn1588 Clock_S for serial connection to external CPUs and syn1588 Clock_M for parallel connection, available in netlist or source code. Synchronization in the nanosecond range over Ethernet is possible. Support for 802.1AS will be available starting summer 2016.

  • syn1588 Clock_M GMII.jpg
  • LAN construction and wiring work
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Error Correction Code "Reed-Solomon Encoder/Decoder"

Error Correction Code "Reed-Solomon Encoder/Decoder"

Error correction code with the option to add bit/byte interleaving function.

The "Reed-Solomon Encoder/Decoder" is an IP core for error correction coding/decoding using the Reed-Solomon method, which is used to improve communication quality in a wide range of fields such as wireless devices, xDSL modems, and digital TVs. It supports variable data block lengths. 【Features】 ■ Supports variable data block lengths ■ The number of check bits, primitive polynomial, and generator polynomial can be customized according to your requirements ■ Additional bit/byte interleaving functionality is also possible *For more details, please refer to the PDF document or feel free to contact us.

  • Other network tools
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TOE10G-IP core for FPGA

TOE10G-IP core for FPGA

Achieving 10 times faster 10GbE TCP/IP communication functionality with pure hardware logic without CPU!

The 10GbE TCP Offloading Engine IP Core (TOE10G-IP) is a groundbreaking solution that allows complex TCP transmission and reception processing, which traditionally required expensive high-end CPUs, to be implemented solely with pure hardware logic without a CPU. It comes standard with a reference design compatible with Xilinx/Intel FPGAs, which can help shorten product development time.

  • ASIC
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USB 3.0 IP core for FPGA

USB 3.0 IP core for FPGA

With the USB3.0 IP core, it is possible to develop a highly versatile FAT32 data recorder in a short period of time!

The 【USB3.0-IP】 complies with the USB3.0 standard Revision 1.0 and includes both the link layer and protocol layer, making it easy to implement a USB3.0 interface when combined with an external PHY chip from TI. A reference design compatible with Xilinx/Altera FPGAs is included as standard with the core product, which can help shorten product development time.

  • ASIC
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TOE40G-IP core for FPGA

TOE40G-IP core for FPGA

Achieving 40 times speed 10GbE TCP/IP communication functionality with pure hardware logic without CPU!

The 40GbE TCP Offloading Engine IP Core (TOE40G-IP) is a groundbreaking solution that enables the complex TCP transmission and reception processes, which traditionally required expensive high-end CPUs, to be implemented solely with pure hardware logic without a CPU. It comes standard with a reference design compatible with Xilinx/Intel FPGAs, which can help shorten product development time.

  • ASIC
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UHF Band RFID Reader/Writer Module【TPURID2100】

UHF Band RFID Reader/Writer Module【TPURID2100】

Space-saving design of 41×32×5.3mm. Control of 920MHz band RFID with MicroPython expands the possibilities of embedded devices.

- High-performance module equipped with the latest chip from Impij - Compact and energy-efficient, making it easy to embed - Capable of standalone operation with MicroPython - Easily combinable with sensors and communication modules - Ideal for inventory management and history management, and can be utilized in a wide range of scenes such as apparel, logistics, and distribution.

  • High frequency/microwave parts
  • RFID/IC tags
  • Other embedded systems (software and hardware)
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2.4GHz band wireless module [TPBPM]

2.4GHz band wireless module [TPBPM]

Accelerate IoT development with MicroPython! A compact 2.4GHz wireless module that achieves low power consumption with LPWA compatibility.

TPBPM is a compact, lightweight, and low power consumption 2.4GHz wireless module. It supports a unique (FSK modulation) mode and BLE. It is equipped with MicroPython, allowing sensors to be directly attached and operate independently. We offer a starter kit that makes it easy to verify the module's operation.

  • Other electronic parts
  • Communications
  • Embedded system design service
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CoaXPress IP Core

CoaXPress IP Core

It is designed to be compact so that the necessary space for the application can be secured on the FPGA.

We would like to introduce the 'CoaXPress IP Core' that we handle. The CoaXPress interface provides a series of IP cores and development frameworks for building FPGA-based transmitters. Additionally, the CXP core is compatible with AMD 7 series (and later), Intel Cyclone V devices (and later), and Microchip PolarFire series. 【Features】 ■ Minimizes development time ■ Achieves top-class performance with a minimal footprint ■ Ensures sufficient flexibility to customize designs ■ Receives all data output from video sensors to CXP PHY ■ Implements control channels according to CXP specifications *For more details, please download the PDF or feel free to contact us.

  • Other production and development software and systems
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USB3 Vision IP Core

USB3 Vision IP Core

For engineers aiming for product development in the short to medium term! Compact and customizable.

We would like to introduce our "USB3 Vision IP Core." We provide a set of IP cores and development frameworks for building FPGA-based products using the USB3 Vision interface. It is also compatible with AMD 7 series devices (and later) and Intel Cyclone V devices (and later). 【Features】 ■ Minimizes development time while achieving top-class performance with a small footprint ■ Ensures sufficient flexibility to customize designs ■ Option to have the source code of the embedded USB3 Vision library running on the Cypress FX3 USB controller *For more details, please download the PDF or feel free to contact us.

  • Other production and development software and systems
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MIPI CSI-2 Receiver IP Core

MIPI CSI-2 Receiver IP Core

Helps connect MIPI sensors from various vendors to FPGA!

We offer the 'MIPI CSI-2 Receiver IP Core', which allows for easy camera design. It is provided as encrypted VHDL, and the VHDL source code is available as an option. Additionally, the MIPI CSI-2 receiver IP software library is provided as an object file, with the option to obtain it as C source code. 【Features】 ■ Compatible with AMD Artix7, Kintex7, Zynq7, and Ultrascale+ FPGAs ■ Comes with a complete reference design for S2I's MVDK equipped with Zynq7 or Ultrascale+ FPGA and IMX MIPI FMC module ■ Easy to port designs to other FPGA platforms *For more details, please download the PDF or feel free to contact us.

  • Other production and development software and systems
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IntelliProp's IP cores for FPGA and ASIC.

IntelliProp's IP cores for FPGA and ASIC.

Providing high-quality and high-performance IP core products for the storage industry! Supporting the development of ASSP products as well.

IntelliProp develops high-quality and high-performance IP core products and ASSP products for the storage industry. Since its establishment in 1998, the company has been providing competitive IP core products as a leading company in specialized fields such as SATA, SAS, PCIe/NVMe, NAND flash, security/encryption, and RAID technology in Longmont, Colorado, USA, where major companies in the storage industry gather. *For more details, please refer to the PDF document or feel free to contact us.*

  • Embedded Board Computers
  • Other network tools
  • Other embedded systems (software and hardware)
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IP cores for FPGA and ASIC manufactured by System-On-Chip.

IP cores for FPGA and ASIC manufactured by System-On-Chip.

High quality, low latency, power-saving IP Core

Providing a group of MPEG standard codecs as IP Cores with high quality, low latency, low power consumption, and a small footprint. Available in Intel FPGA and Xilinx versions.

  • Embedded Board Computers
  • Other network tools
  • Other embedded systems (software and hardware)
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IP core "AndesCore AX25"

IP core "AndesCore AX25"

64-bit CPU architecture! It can access an address space significantly exceeding 4GB.

The "AndesCore AX25" is a compact 64-bit CPU IP core based on the AndeStar V5 architecture, which incorporates RISC-V technology. It is optimized for high-performance embedded applications that require access to an address space exceeding 4GB. Options such as branch prediction for efficient branch instruction execution, instruction and data caches, local memory for low-latency access, and ECC for L1 memory soft error protection are available. 【Specifications (partial)】 ■ AndeStar V5 Instruction Set Architecture (ISA) utilizing RISC-V technology ■ DSP/SIMD ISA suitable for digital signal processing ■ Floating-point extension ■ Andes extensions that enable high performance and high functionality *For more details, please refer to the related links or feel free to contact us.

  • ASIC
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SATA Host APP for FPGA and ASIC IP Cores

SATA Host APP for FPGA and ASIC IP Cores

Equipped with a self-test! Supports power modes (partial/slumber).

We would like to introduce our "SATA Host APP IP Core for FPGA and ASIC." This is an IP core for SATA hosts that complies with the SATA 3.3 standard and supports a maximum transfer rate of 6Gbps (600MB/s). It consists of the PHY layer, LNK layer, TRN (Transport) layer, application layer, SerDes, and FIFO interface. 【Specifications】 ■ Complies with SATA Revision 3.3 standard (1.5Gbps, 3.0Gbps, 6.0Gbps) ■ Supports OOB (Out of Band) ■ Uses FIFO for the DATA interface ■ Supports either SerDes, PIPE, or SAPIS interfaces ■ Supports power modes (partial/slumber) ■ Equipped with self-test functionality *For more details, please download the PDF or feel free to contact us.

  • ASIC
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SATA Host AHCI IP Core for FPGA/ASIC

SATA Host AHCI IP Core for FPGA/ASIC

It can widely support systems that require a SATA host!

The "IP Core SATA Host AHCI for FPGA/ASIC" complies with the SATA 3.3 standard and supports a maximum transfer rate of 6Gbps (600MB/s) for SATA hosts. With the AHCI interface, it can be easily connected using standard drivers. Additionally, it consists of the SATA core [Phy layer, LNK layer, TRN (Transport) layer], SATA host application, and AHCI layer. 【Specifications (Excerpt)】 ■ Complies with SATA Revision 3.3 standard (1.5Gbps, 3.0Gbps, 6.0Gbps) ■ Supports OOB (Out of Band) ■ Supports either SerDes, PIPE, or SAPIS interfaces ■ Supports power modes (partial/slumber) ■ Equipped with self-test functionality *For more details, please download the PDF or feel free to contact us.

  • ASIC
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SAS Initiator IP Core for FPGA/ASIC

SAS Initiator IP Core for FPGA/ASIC

OOB sequence and speed negotiation sequence support!

The "IP Core SAS Initiator for FPGA/ASIC" complies with the SAS 3.0 standard and supports a maximum transfer rate of 12Gbps (1200MB/s) for Serial-SCSI (SAS) initiators (hosts). It consists of four blocks (Phy layer, LINK layer, PORT layer, TRN layer), along with a processor, SerDes, and memory interface. It is designed to connect to SAS-compliant device applications to transmit and receive OOB signals, primitives, and SAS frames. 【Specifications (Excerpt)】 ■ Compliant with SAS 3.0 standard ■ Supports SAS 3.0Gbps, 6.0Gbps, and 12.0Gbps ■ Register access to link layer/transport layer ■ Supports SerDes, PIPE, and SAPIS interfaces ■ Supports OOB sequence and speed negotiation sequence *For more details, please download the PDF or feel free to contact us.

  • ASIC
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IP core for FPGA/ASIC NVMe Target

IP core for FPGA/ASIC NVMe Target

Register access from the processor is available! Command interrupt support is included.

We would like to introduce the 'FPGA/ASIC IP Core for NVMe Target' handled by Fujisoft Inc. It is equipped with NVMe command queuing response functionality, allowing it to be used in high-performance storage products that take advantage of NVMe's high data transfer speeds. This is an IP core for NVMe targets that complies with the NVMe 1.4 specification and operates on PCIe 4.0 (8Gbps) x 8 lanes. 【Specifications (Excerpt)】 ■ Compliant with NVM Express 1.4 specification ■ Compatible with third-party PCIe Root Complex IP cores ■ Application layer with an interface to the processor ■ FIFO data interface ■ Register access from the processor is possible *For more details, please download the PDF or feel free to contact us.

  • ASIC
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