We have compiled a list of manufacturers, distributors, product information, reference prices, and rankings for IP Cores.
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IP Cores Product List and Ranking from 29 Manufacturers, Suppliers and Companies

Last Updated： Aggregation Period:Sep 17, 2025～Oct 14, 2025
This ranking is based on the number of page views on our site.

IP Cores Manufacturer, Suppliers and Company Rankings

Last Updated： Aggregation Period:Sep 17, 2025～Oct 14, 2025
This ranking is based on the number of page views on our site.

  1. 富士ソフト インダストリービジネス事業部 Kanagawa//software
  2. デザイン・ゲートウェイ Tokyo//Electronic Components and Semiconductors
  3. Euresys Japan ユレシス　ジャパン Kanagawa//Electronic Components and Semiconductors
  4. 4 NSCore Fukuoka//Electronic Components and Semiconductors
  5. 5 サイレックス・テクノロジー Kyoto//Other manufacturing
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IP Cores Product ranking

Last Updated： Aggregation Period:Sep 17, 2025～Oct 14, 2025
This ranking is based on the number of page views on our site.

  1. Wireless LAN Survey "WM-100" サイレックス・テクノロジー
  2. A system to notify when passing by to prevent forklift accidents in the factory. パシフィック湘南
  3. MTP non-volatile memory IP core 'TwinBit' NSCore
  4. NVMe IP core for FPGA デザイン・ゲートウェイ
  5. 4 IP cores for FPGA and ASIC manufactured by System-On-Chip. 富士ソフト インダストリービジネス事業部

IP Cores Product List

16～30 item / All 101 items

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SATA IP core for FPGA

SATA IP core for FPGA

High-performance, high-reliability IP core proven by NASA (National Aeronautics and Space Administration).

The Serial ATA (SATA) IP core complies with Serial ATA Revision 3.0 and is designed to operate on FPGA devices such as Xilinx UltraScale, 7 Series, and Intel 10 Series. This IP core provides only the link layer, but reference designs for the transport layer and physical layer are available, allowing connection to SATA3 hard disks without a PHY chip. This SATA IP core maximizes the performance of SSDs, enabling high-speed transfers exceeding 500MB/s per channel. Limited-time evaluation demo files for various FPGA boards are prepared, allowing performance evaluation on actual hardware before purchase. Additionally, the core product comes standard with reference designs that operate on various Xilinx/Intel FPGA evaluation boards, enabling development to start based on this reference design, which allows for rapid product development.

  • ASIC

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UDP 10G IP Core for FPGA

UDP 10G IP Core for FPGA

Achieving 10Gbps UDP communication functionality with pure hardware logic without CPU!

The 【UDP10G IP Core】 is a groundbreaking solution that allows UDP transmission and reception processing to be implemented solely with pure hardware logic, without the need for a CPU. It also supports high-speed simultaneous transmission and reception. This can help shorten the development time for network application products that require broadcasting and low latency. Additionally, we have prepared demo files for Xilinx/Intel FPGA evaluation boards, allowing you to evaluate and test this core on actual hardware before purchase.

  • ASIC

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25G TOE IP core for FPGA

25G TOE IP core for FPGA

Achieving 25G TCP/IP communication functionality with pure hardware logic without CPU!

The 25GbE TCP Offloading Engine IP Core (TOE25G-IP) is a groundbreaking solution that enables the complex TCP transmission and reception processes, which traditionally required expensive high-end CPUs, to be implemented solely with pure hardware logic without a CPU. It comes standard with a reference design compatible with Xilinx/Intel FPGAs, which can help shorten product development time. It provides 25G performance and bandwidth, which is 2.5 times that of the conventional 10G in a single channel. This significantly reduces power consumption and cost per gigabit.

  • ASIC

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TOE100G-IP core for FPGA

TOE100G-IP core for FPGA

Achieving 100G TCP/IP communication functionality with pure hardware logic without CPU!

The 100GbE TCP Offloading Engine IP Core (TOE100G-IP) is a groundbreaking solution that enables the implementation of complex TCP transmission and reception processes, which traditionally required expensive high-end CPUs, using only pure hardware logic without a CPU. It comes standard with a reference design compatible with Xilinx/Intel FPGAs, which can help shorten product development time.

  • ASIC

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LDPC IP core

LDPC IP core

We provide a total solution for LDPC codes, from system design and computer simulation evaluation to IP macros.

LDPC (Low Density Parity Check) symbols LDPC symbols have error correction capabilities that are extremely close to the Shannon limit, and they are error correction codes that enable high-speed processing of codes through parallel processing. Features of Mobile Tech's LDPC Symbol Total Solution We provide Encoder/Decoder IPs with optimal configurations based on the required performance (circuit scale/througput) that support standard LDPC codes as well as customer-specific LDPC codes, and we also design and support peripheral modules to maximize performance.

  • Other network tools

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IP Core Catalog

IP Core Catalog

Includes practical reference designs! A wide variety of lineups are available.

This catalog introduces the "IP cores" handled by Euresys Japan Co., Ltd. It includes various products such as the compact and customizable "GigE Vision IP core," the "USB3 Vision IP core" with practical reference designs, and the "CoaXPress IP core." Please use this for selecting products. 【Featured Products (partial)】 ■ CoaXPress-over-Fiber Bridge IP core ■ GigE Vision IP core ■ USB3 Vision IP core ■ CoaXPress IP core ■ IMX Pregius IP core, etc. *For more details, please refer to the PDF document or feel free to contact us.

  • others

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Northwest Logic's IP cores for FPGA and ASIC.

Northwest Logic's IP cores for FPGA and ASIC.

Achieving high performance and high quality of standalone controller IP cores, in collaboration with PHY IP vendors and verification IP vendors!

Northwest Logic has been providing controller IP cores focused on memory interfaces, MIPI, and PCI Express since its establishment in 1995. For memory interfaces, we offer a wide range of controllers including HBM2, DDR4/3, and LPDDR4, as well as CSI-2 and DSI-2/DSI for MIPI, and Gen4/3 for PCI Express. Our customizable IP cores are equipped with the full functionality of each protocol and are compatible with both ASIC and FPGA platforms. In addition to achieving high performance and quality for standalone controller IP cores through extensive simulation and hardware verification, we also focus on collaboration with PHY IP vendors and verification IP vendors, enabling us to provide total solutions for customers looking to integrate memory interfaces, MIPI, and PCI Express functionalities into their systems. *For more details, please refer to the PDF materials or feel free to contact us.

  • Other network tools
  • Other embedded systems (software and hardware)

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SATA Device ADCI IP Core for FPGA and ASIC

SATA Device ADCI IP Core for FPGA and ASIC

Supports power modes (partial/slumber)! The DATA interface uses FIFO.

We would like to introduce our "FPGA/ASIC IP Core for SATA Device ADCI." This is an IP core for SATA devices that complies with the SATA 3.3 standard and supports a maximum transfer rate of 6Gbps (600MB/s). It features an ADCI (Advanced Device Controller Interface) that allows for easy operation via processors/firmware, making it suitable for a wide range of SATA storage device solutions. 【Specifications (Excerpt)】 ■ Complies with SATA Revision 3.3 standard (1.5Gbps, 3.0Gbps, 6.0Gbps) ■ Supports Application layer, Transport layer, Link layer, and Phy layer, including ADCI ■ Supports OOB (Out of Band) ■ Uses FIFO for DATA interface *For more details, please download the PDF or feel free to contact us.

  • ASIC

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SATA RAID IP Core for FPGA and ASIC

SATA RAID IP Core for FPGA and ASIC

Fully compliant with SATA industry specifications! Operates with drives that are multiples of 2.

The "IP Core for SATA RAID for FPGA/ASIC" provides RAID 0 (striping and concatenation) and splits data across multiple storage endpoints to achieve higher system storage performance. It is designed to operate with extremely low latency during data transfers between SATA storage devices and backend data interfaces. This can be used for RAID 0 storage solutions that require high speed and large capacity. 【Specifications (excerpt)】 - Supports RAID 0 (striping and concatenation) - Operates with an even number of drives - SATA transfer rates: 1.5Gbps, 3.0Gbps, and 6.0Gbps (supports automatic speed negotiation) *For more details, please download the PDF or feel free to contact us.

  • ASIC

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NVMe Host Accelerator IP Core

NVMe Host Accelerator IP Core

It is an application layer equipped with an interface to the processor!

We would like to introduce the "NVMe Host Accelerator IP Core" that we handle. This product is an NVMe host IP core from IntelliProp that complies with the NVMe 1.4 specification and operates on PCIe 4.0 (8Gbps) with 8 lanes. It also features queuing and issuing capabilities for NVMe commands, allowing you to use it as a solution for high-speed data access to NVMe target devices. 【Specifications (excerpt)】 ■ Compliant with NVM Express 1.4 specification ■ Supports automatic initialization using PCIe hard blocks ■ Compatible with third-party PCIe Root Complex IP cores ■ Number of queues is adjustable (up to 64K) ■ Maximum data buffer size of 1GB *For more details, please download the PDF or feel free to contact us.

  • ASIC

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NVMe-to-NVMe Bridge

NVMe-to-NVMe Bridge

Supports automatic initialization using PCIe hard blocks!

The "NVMe-to-NVMe Bridge" is an NVMe bridge IP core that creates an NVMe protocol bridge using NVMe Host IP cores and NVMe Target IP cores. In this architecture, a sandbox area is implemented in the bridge, allowing for the implementation of custom logic and firmware. It can be used for purposes such as LBA remapping, data encryption, data compression, and endpoint aggregation. 【Specifications】 ■ Compliant with NVM Express 1.4 standard ■ Compatible with third-party PCIe Root Complex IP cores ■ Supports automatic initialization using PCIe hard blocks ■ Automated command transmission and completion ■ Application layer with an interface to the processor *For more details, please download the PDF or feel free to contact us.

  • ASIC

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AES-GCM Encryption IP Core

AES-GCM Encryption IP Core

Multiple independent data streams! You can choose the AES encryption key from 128 or 256 bits.

We would like to introduce the 'AES-GCM Encryption IP Core' that we handle. This is an AES-GCM (Galois Counter Mode) encryption IP core that enables users to perform encryption/decryption and authentication of packets or data streams. It supports AES-GCM encryption levels of 128 or 256 bits and is capable of data throughput supporting SATA 6Gbps, SAS 12Gbps, PCIe (NVMe) Gen4 x4 lanes, and Ethernet 10Gbps and 25Gbps. 【Specifications】 ■ AES encryption key selectable from 128 or 256 bits ■ Internal Hamming ECC protection/correction for internal memory ■ Multiple independent data streams ■ Key expansion caching to optimize packet performance ■ Packet queuing for optimal throughput *For more details, please download the PDF or feel free to contact us.

  • ASIC

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FPGA-compatible MECHATROLINK communication IP 'SYM3A'

FPGA-compatible MECHATROLINK communication IP 'SYM3A'

Mechatrolink communication macros can be implemented on intel-FPGA.

This is a soft IP that enables the implementation of the MECHATOROLINK-III communication protocol on FPGA. It flexibly accommodates the addition of various interfaces and peripheral circuits, which are features of FPGAs, and allows for easy design integration using the GUI of the Qsys system integration tool. The basic functionality of this IP is equivalent to Yaskawa Electric's JL-100/JL-102. It is easy to build an evaluation environment by combining the Macnica Sodia board with our SY-M3-03 board. High functionality and high-speed processing are achieved through cooperative operation between the ARM Cortex-A9 and user circuits (ARM is used when employing Intel FPGA SoC). * Operation has been confirmed on the Macnica Sodia-Cyclone V ST SoC evaluation board. ■ Supports C1 master/slave/multi-slave configurations ■ Netlist provided as a Soft-IP core ■ MECHATROLINK-III certification obtained

  • Other semiconductors

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High-speed reversible data compression IP core for FPGA 'CVC Codec'

High-speed reversible data compression IP core for FPGA 'CVC Codec'

To streamline system research and development! Efficiently compress measurement data to contribute to the development of autonomous driving technology.

The "CVC Codec" is an IP library that implements our original lossless data compression algorithm, CVC method, specialized for natural information such as image data and waveform data on FPGA. It features a compact circuit size, making it easy to implement into existing systems. The processing speed is stable, providing excellent real-time performance. Additionally, it boasts a higher compression ratio compared to conventional lossless compression. 【Features】 ■ Efficiently compresses measurement data, contributing to the development of autonomous driving technology ■ Achieves overwhelming high-speed processing ■ Compression starts instantly after data input, with low latency design ■ Stable processing speed, excelling in real-time performance ■ Easy implementation into existing systems with a compact circuit size *For more details, please refer to the PDF materials or feel free to contact us.

  • others

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