Last Updated： Aggregation Period:Jul 23, 2025～Aug 19, 2025
This ranking is based on the number of page views on our site.
Last Updated： Aggregation Period:Jul 23, 2025～Aug 19, 2025
This ranking is based on the number of page views on our site.
Last Updated： Aggregation Period:Jul 23, 2025～Aug 19, 2025
This ranking is based on the number of page views on our site.
1～15 item / All 81 items
Sprite Drawing IP Core (Verilog)
This process overlays character images (sprites) onto a background image. The maximum image size is 1024x1024. Arbitrary angle rotation in 0.35-degree increments. During rotation, a bi-linear interpolated image is created. Mirror flipping. Alpha blending. The maximum number of overlays is 16.
Enlarge/Reduce IP Core (Verilog)
P1_Scale performs image scaling using multi-rate signal processing in hardware. The maximum image size is 1024x1024, and the scaling ratio is N/M where N and M can be 1, 2, 3, 4, 5, 6, 7, or 8.
JPEG compression IP core (Verilog)
Verilog-HDL JPEG compression IP core Compression method: JPEG Base Line method Input format: RGB 8:8:8 Output format: YUV 4:2:0 4:2:2 4:4:4 Huffman coding: Standard settings (Annex K) used Can also be set in registers Quantization table: Standard settings (Annex K) used Can also be set in registers
No need for complex memory cell configurations! We provide high-performance non-volatile memory at low manufacturing costs.
"TwinBit" is a non-volatile memory IP core that can be manufactured using standard logic processes. It is capable of over 100,000 write cycles across a wide range of processes, from the 0.18um generation to advanced 16nm generation and beyond. It provides high-performance non-volatile memory at a low manufacturing cost without requiring the complex memory cell configurations typical of conventional Flash memory. Customization is also available for various non-volatile memory core applications, ranging from 64-bit latch types to 2MByte code storage memory. 【Features】 ■ World-class smallest memory cell size ■ High-speed, low-power read operation ■ Low-voltage write operation ■ Built-in test circuits *For more details, please refer to the PDF document or feel free to contact us.
Significant power consumption reduction has been achieved through partial CMOS logic implementation at the physical layer and low-voltage support at the logic layer.
SLIPHDMILPT is an IP core designed for mobile devices, reduced to a power consumption of 100mW or less (40mW or less for the physical layer only).
It can be easily integrated into SoCs such as HD TVs and AV receivers.
The HDMI receiver link IP core "SLISIHDMI" complies with the HDMI 1.3a standard, and when connected to the HDMI Receiver PHY IP SLIPHDMIR, it can most efficiently leverage the performance of the SLISIHDMIR HDMI Rx IP. Additionally, it is possible to customize the functions of the SLISIHDMIR HDMI Rx IP according to your requirements. For more details, please contact us.
High-speed Reed-Solomon achieving a throughput of over 1 Gbps.
The "Lead Solomon Express" is an error correction encoding/decoding (Encoder/Decoder) IP core that achieves a throughput of over 1 Gbps by pipeline processing the calculation of error location polynomials and error values. It supports variable data block lengths. 【Features】 ■ Achieves a throughput of over 1 Gbps ■ Supports variable data block lengths ■ The number of check bits, primitive polynomials, and generator polynomials can be customized according to your requirements. *For more details, please refer to the PDF document or feel free to contact us.
Supports PCIe Gen4 SSD, no external memory required, 2ch RAID0, compatible with random access.
The NVMe IP core is an IP core that interfaces next-generation storage PCIe SSDs, which serve as a replacement for SATA SSDs, with FPGAs without the need for a CPU or external memory. A reference design that operates on various Xilinx/Intel FPGA evaluation boards is included as standard, allowing development to start based on this reference design, enabling rapid product development. This NVMe IP core maximizes the performance of NVMe PCIe SSDs, achieving high-speed transfers of over 3300MB/s (evaluated with KCU105 and Samsung 970 Pro). Time-limited bit/sof files for various Xilinx/Intel FPGA boards are prepared, allowing performance evaluation on actual hardware before purchase.
High-performance, high-reliability IP core proven by NASA (National Aeronautics and Space Administration).
The Serial ATA (SATA) IP core complies with Serial ATA Revision 3.0 and is designed to operate on FPGA devices such as Xilinx UltraScale, 7 Series, and Intel 10 Series. This IP core provides only the link layer, but reference designs for the transport layer and physical layer are available, allowing connection to SATA3 hard disks without a PHY chip. This SATA IP core maximizes the performance of SSDs, enabling high-speed transfers exceeding 500MB/s per channel. Limited-time evaluation demo files for various FPGA boards are prepared, allowing performance evaluation on actual hardware before purchase. Additionally, the core product comes standard with reference designs that operate on various Xilinx/Intel FPGA evaluation boards, enabling development to start based on this reference design, which allows for rapid product development.
Achieving 10Gbps UDP communication functionality with pure hardware logic without CPU!
The 【UDP10G IP Core】 is a groundbreaking solution that allows UDP transmission and reception processing to be implemented solely with pure hardware logic, without the need for a CPU. It also supports high-speed simultaneous transmission and reception. This can help shorten the development time for network application products that require broadcasting and low latency. Additionally, we have prepared demo files for Xilinx/Intel FPGA evaluation boards, allowing you to evaluate and test this core on actual hardware before purchase.
