ストラテジー Product Lineup

"HDL Auto SpecDraw" analyzes source code written in Verilog-HDL/VHDL languages. [Are you facing these issues?] "Only the source code remains, with no comments." "There is no design specification document, and it's disorganized." "Additional modifications are not reflected in the documentation." "The behavior changed in places different from where the changes were made." "The designer is no longer available, and no one understands." ★Even for analysis, we can no longer allocate the time of skilled engineers! [Features] ■Draw multiple source files within the same project in a schematic style 　⇒Visually capture the entire project ■Highlight any signal lines 　⇒Trace the connections of modules ■Output various reports 　⇒Support analysis *For more details, please refer to the PDF materials or feel free to contact us.

• Other analyses
• ASIC
• Other semiconductors

"StrategyTimeChartSTD" is a design support tool that thoroughly pursues ease of use. Basic operations, such as waveform drawing, can be easily performed with a mouse. It smartly and comprehensively supports the functions that developers working in the field need, such as automatic waveform generation and timing violation detection. It also supports files from various design tools and measurement devices, allowing for immediate integration into existing design, analysis, and review workflows. 【Features】 - Easily draw beautiful timing charts - Automatically generate waveforms for clocks, buses, and counters - Automatically generate waveforms from logical expressions, truth tables, and pattern notations - Capable of drawing sine waves, capacitor charge/discharge waveforms, and digital four-value representations - A variety of editing functions For more details, please contact us or download the catalog.

• Development support tools (ICE, emulators, debuggers, etc.)