デザイン・ゲートウェイ Product Lineup

The 100GbE TCP Offloading Engine IP Core (TOE100G-IP) is a groundbreaking solution that enables the implementation of complex TCP transmission and reception processes, which traditionally required expensive high-end CPUs, using only pure hardware logic without a CPU. It comes standard with a reference design compatible with Xilinx/Intel FPGAs, which can help shorten product development time.

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The 25GbE TCP Offloading Engine IP Core (TOE25G-IP) is a groundbreaking solution that enables the complex TCP transmission and reception processes, which traditionally required expensive high-end CPUs, to be implemented solely with pure hardware logic without a CPU. It comes standard with a reference design compatible with Xilinx/Intel FPGAs, which can help shorten product development time. It provides 25G performance and bandwidth, which is 2.5 times that of the conventional 10G in a single channel. This significantly reduces power consumption and cost per gigabit.

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The NVMe IP core is an IP core that interfaces next-generation storage PCIe SSDs, which serve as a replacement for SATA SSDs, with FPGAs without the need for a CPU or external memory. A reference design that operates on various Xilinx/Intel FPGA evaluation boards is included as standard, allowing development to start based on this reference design, enabling rapid product development. This NVMe IP core maximizes the performance of NVMe PCIe SSDs, achieving high-speed transfers of over 3300MB/s (evaluated with KCU105 and Samsung 970 Pro). Time-limited bit/sof files for various Xilinx/Intel FPGA boards are prepared, allowing performance evaluation on actual hardware before purchase.

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The 40GbE TCP Offloading Engine IP Core (TOE40G-IP) is a groundbreaking solution that enables the complex TCP transmission and reception processes, which traditionally required expensive high-end CPUs, to be implemented solely with pure hardware logic without a CPU. It comes standard with a reference design compatible with Xilinx/Intel FPGAs, which can help shorten product development time.

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The 【UDP10G IP Core】 is a groundbreaking solution that allows UDP transmission and reception processing to be implemented solely with pure hardware logic, without the need for a CPU. It also supports high-speed simultaneous transmission and reception. This can help shorten the development time for network application products that require broadcasting and low latency. Additionally, we have prepared demo files for Xilinx/Intel FPGA evaluation boards, allowing you to evaluate and test this core on actual hardware before purchase.

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The 10GbE TCP Offloading Engine IP Core (TOE10G-IP) is a groundbreaking solution that allows complex TCP transmission and reception processing, which traditionally required expensive high-end CPUs, to be implemented solely with pure hardware logic without a CPU. It comes standard with a reference design compatible with Xilinx/Intel FPGAs, which can help shorten product development time.

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The 【AB17-M2FMC】 is an adapter board that converts 8 channels of high-speed differential signals (DP0-DP7) from the FMC expansion interface into two 4-lane PCI standard M.2 interfaces. It can be applied to various evaluation boards from Intel/Xilinx that implement the FMC interface. Additionally, this adapter is required when evaluating the NVMe-IP core from DesignGateway.

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The 【AB16-PCIeXOVR】 is a conversion adapter board for host-device connections that supports 1/4/8-lane PCIe (PCI-Express) and can be applied to evaluation boards from Intel/Xilinx that implement the PCIe interface. The adapter board features 8-lane PCIe sockets on both the component side and the solder side, directly connecting the transmit and receive signals lane by lane to function as host side/device side. This adapter is ideal for developing FPGA applications that implement PCIe host side functionality. Additionally, this adapter is required when evaluating the NVMe-IP core from DesignGateway.

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The 【SDLink SL001】 is an FPGA configuration module that stores circuit data on a microSD memory card. It supports 2GB microSD cards and provides virtually unlimited space for FPGA circuit data, with a maximum of 16Gbit. Additionally, it can store circuit data for up to 8 FPGAs and allows for simultaneous configuration. Updating FPGA circuit data in the field is made very easy by swapping the microSD card.

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• Memory

IPLock is an FPGA logic security system that employs highly reliable AES encryption technology. By integrating the IP Lock logic into user logic and mounting a security chip in SOIC-8 size onto the user board, it protects the IP assets within the FPGA from illegal duplication.

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• Encryption and authentication

The Serial ATA (SATA) IP core complies with Serial ATA Revision 3.0 and is designed to operate on FPGA devices such as Xilinx UltraScale, 7 Series, and Intel 10 Series. This IP core provides only the link layer, but reference designs for the transport layer and physical layer are available, allowing connection to SATA3 hard disks without a PHY chip. This SATA IP core maximizes the performance of SSDs, enabling high-speed transfers exceeding 500MB/s per channel. Limited-time evaluation demo files for various FPGA boards are prepared, allowing performance evaluation on actual hardware before purchase. Additionally, the core product comes standard with reference designs that operate on various Xilinx/Intel FPGA evaluation boards, enabling development to start based on this reference design, which allows for rapid product development.

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The 【AB09-FMCRAID】 is an FMC board for RAID development that conforms to the FMC standard and converts high-speed serial channels of HPC (High Pin Count) into up to 10 channels of SATA interfaces. It is compatible with various Xilinx official evaluation boards and is ideal for developing RAID systems using SATA-IP cores.

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The TCP Offloading Engine IP Core (TOE1G-IP) is a groundbreaking solution that enables the complex TCP transmission and reception processes, which traditionally required expensive high-end CPUs, to be implemented solely with pure hardware logic without a CPU. It comes standard with a reference design compatible with Xilinx/Altera FPGAs, which can help shorten product development time.

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The 【USB3.0-IP】 complies with the USB3.0 standard Revision 1.0 and includes both the link layer and protocol layer, making it easy to implement a USB3.0 interface when combined with an external PHY chip from TI. A reference design compatible with Xilinx/Altera FPGAs is included as standard with the core product, which can help shorten product development time.

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The 【AB07-USB3FMC】 is an FMC mezzanine card designed to connect with Xilinx evaluation boards featuring FMC-LPC (Low Pin Count) or FMC-HPC (High Pin Count) connectors, allowing for the real-world evaluation of the USB3.0-IP from DesignGateway. This demo board can be used for evaluating both the device-side IP core (product model number: USB3D-IPxxx) and the host-side IP core (product model number: USB3H-IPxxx). By combining the Xilinx core evaluation board with this demo board and using the evaluation bit file, it is possible to confirm the operation of USB3.0 SuperSpeed transfers in your own environment. * Please note that the FMC interface voltage of this demo board is fixed at 2.5V, so it cannot be used with Xilinx evaluation boards (such as VC709) that cannot be set to 2.5V. * This product is exclusively for users of the DG USB3.0 IP core.

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• Board to Board Connectors