[Finished] On June 3rd (Friday), at the JIEP Advanced Implementation Technology Symposium (Tokyo Big Sight), we introduced the wafer process technology for 3D stacking/TSV formation by Zeiss Microtech.

On June 3rd (Friday), at Tokyo Big Sight, we will introduce the wafer process technology for 3D stacking from Zeus Microtech at the JIEP Advanced Implementation Technology Symposium/Session 3A1 "New Implementation Technologies for Next-Generation 3D Packages" (9:30–12:30).
Development of 3D stacked devices using TSV is progressing in fields such as CMOS image sensors and MEMS. We will present on the lithography, thin wafer handling (temporary bonding/debonding), and wafer bonding technologies necessary for 3D stacking/integration.
In this seminar, experts from various fields will also give presentations on the latest technologies in 3D implementation and next-generation packaging.
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