Free Webinar: In a nutshell, FPGA Design Verification Part 3

With the evolution of FPGA technology, the traditional programmable logic domain has expanded to include CPUs, GPUs, and high-speed peripherals, making design verification increasingly difficult. Relying solely on physical verification for FPGA testing is clearly insufficient for safety-critical designs, and FPGA teams are adopting advanced design verification methodologies and techniques to develop their own verification processes. In this final installment of the webinar series, we will introduce advanced verification solutions such as scoreboards, checkers, functional coverage, and assertions. We will also cover transaction-based debugging and unit linting features, as well as regression testing using Riviera-PRO.

Date and time | Wednesday, Jan 29, 2025 03:00 PM ~ 04:00 PM |
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Entry fee | Free |
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