Free Webinar: OOP for Hardware Designers

~ Understanding SystemVerilog Objects ~
Many hardware designers use RTL design techniques for the development of various applications. However, the verification of large-scale designs requires higher levels of abstraction, such as functional coverage, constrained random, and UVM. To achieve this, object-oriented programming (OOP) is essential, but hardware designers often have limited opportunities and time to engage with it. In this seminar, we will introduce SystemVerilog classes and object-oriented programming using simple examples.

Date and time | Wednesday, Feb 26, 2025 03:00 PM ~ 04:00 PM |
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Entry fee | Free |
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