Free Webinar: VHDL/SystemVerilog RTL Verification Environment with cocotb - Test Benches Written in Python
Cocotb is a coroutine-based co-simulation testbench environment for verifying VHDL and SystemVerilog/Verilog designs using Python. It is an open-source environment hosted on GitHub. It uses the same concepts of reusability and functional verification as UVM, but is implemented in Python. This webinar will provide an overview of cocotb.

| Date and time | Thursday, Apr 17, 2025 03:00 PM ~ 04:00 PM |
|---|---|
| Entry fee | Free |
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