Free Webinar: Let's Challenge UVM!

Typically, hardware designers are very busy and have little time to try out new methodologies. Unfortunately, the official documentation for UVM (Universal Verification Methodology) is written by verification engineers for verification engineers, focusing on high-level functionality while ignoring lower-level details such as connecting the UVM testbench to the design. In this webinar, we will explain the main UVM components such as Sequencer and Driver using a simple design and virtual interfaces.

Date and time | Wednesday, May 21, 2025 03:00 PM ~ 04:30 PM |
---|---|
Entry fee | Free |
Inquiry about this news
Contact Us OnlineMore Details & Registration
Details & Registration