Free Webinar: Let's Use SVA for Requirements-Based Verification of Safety-Critical FPGA Designs!

Requirements-based verification is a common verification process for FPGA designs used in safety-critical systems. The effectiveness of requirements-based verification depends on the quality and accuracy of the requirements. Verification methods such as constraint-based random verification using assertion-based verification help identify ambiguous or incomplete requirements early in the design and verification process. Additionally, assertions can enhance the observability of the design, significantly reducing debugging time. This increases the time available for exploring new bugs, leading to improved verification quality. In this webinar, we will introduce how to optimize and verify requirements using SystemVerilog assertions.

Date and time | Wednesday, Jul 23, 2025 03:00 PM ~ 04:00 PM |
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Entry fee | Free |
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