Aldec enhances VHDL and UVVM support for Riviera-PRO.

Henderson, USA - December 17, 2019 - Aldec, Inc. (hereinafter referred to as "Aldec"), a pioneer in HDL mixed-language simulation and hardware-assisted verification for FPGA and ASIC, has added features to provide further support while working with the latest version of VHDL (2018) and the Universal VHDL Verification Methodology (UVVM) 2019.09.02 release on the Riviera-PRO functional verification platform.

Inquiry about this news
Contact Us OnlineMore Details & Registration
Details & Registration
Related Documents
Related Links
Press Page
Product Page