Improving productivity through methodology: Aldec has added a UVM generator to Riviera-PRO and updated the OSVVM and UVVM libraries.

Henderson, NV – November 16, 2021 – Aldec, Inc. (hereinafter referred to as "Aldec"), a pioneer in HDL mixed-language simulation and hardware-assisted verification with FPGA and ASIC, has added an automatic UVM generator feature to Riviera-PRO. With this addition, it is expected that the productivity of Riviera-PRO users will be significantly improved by leveraging the benefits of the Universal Verification Methodology, which includes guidance on the creation and reuse of verification test benches.
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