Free Webinar: Transaction-Level Modeling Will Surely Be Necessary from Now On

It has become clear that with today's large-scale ASICs/SoCs and FPGAs, traditional RTL modeling techniques alone make design and verification difficult. As a result, the concept of Transaction Level Modeling (TLM) has been widely adopted, and it has become essential in verification methods such as UVM. In this webinar, we will introduce TLM using terminology explanations and implementation examples with simple sample designs.

Date and time | Wednesday, Mar 19, 2025 03:00 PM ~ 04:00 PM |
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Entry fee | Free |
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