Test chip for evaluating Cu bonding with Cu bumps.
Cu bump mounted Cu bonding evaluation test chip ■Wafer size ... 8-inch wafer ■Base chip size ... 5.09mm × 5.09mm ■Pad pitch ... 150μm (staggered pads) ■Number of pads ... 841 bumps ■Compatible bump process ... Cu bump ■Compatible substrate ... None ■Options ... Bump mounting / Dicing processing / Back grinding processing ■Main applications Package development, process startup/development, promotional data acquisition, etc.
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basic information
The JTEG and JKIT from Hitachi Ultra LSI Systems, which we are introducing here, have ceased production of all products as of December 2009. The latest information on Well's original open TEG chip "JCHIP" can be found here: http://well-teg.jp/
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Applications/Examples of results
Our test chips are standard TEG chips developed to support various methods for SIP development, package development, implementation method development, PCB substrate development, implementation and inspection equipment development, and material development applications, and are already being used by over 200 customers both domestically and internationally. We also accept requests for the creation of custom chips with special specifications.
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Company information
Well develops and implements a packaging solution business centered on test chips for advanced implementation evaluation, covering everything from bare chip packaging equipment development and contract implementation to reliability evaluation. ~ Corporate Philosophy ~ ■ With "Profitable Relationship" as the core of our management philosophy, we aim to be a company that contributes to the prosperity of our customers and the development of the globally expanding electronics components industry. ■ Through the provision of products that support next-generation semiconductor packaging development, we contribute to the promotion of our customers' development and the enhancement of their profits. ■ We aim to create valuable markets by providing "innovative products" and "cutting-edge services."
