HES-MPF500-M2S150

The latest release of HES-DVM provides a simulation acceleration flow that significantly speeds up RTL simulation for designs targeting Microchip FPGA devices. Henderson, NV, USA – November 3, 2020 – Aldec, Inc. (hereinafter referred to as "Aldec"), a pioneer in HDL mixed-language simulation and hardware-assisted verification for FPGAs and ASICs, announced the HES-DVM simulation acceleration flow for Microchip Polarfire, SmartFusion2, and RTSX/RTAX FPGA designs using Aldec's HES-MPF500-M2S150 prototyping board. Please refer to the attached document for more details.

Henderson, USA - November 26, 2019 - Aldec, Inc. (hereinafter referred to as "Aldec"), a pioneer in HDL mixed-language simulation and hardware-assisted verification for FPGA and ASIC, has released the HES-MPF500-M2S150 development kit to support the development of FPGA-based embedded systems using either or both Microchip PolarFire or SmartFusion2 family devices. The HES-MPF500-M2S150 development kit is the industry's first product equipped with devices from the Microchip PolarFire and SmartFusion2 FPGA families. All other available development boards feature only one of these, and such single FPGA boards are equipped only with mid-range devices.