Aldec announces hardware-assisted RTL simulation acceleration for Microchip FPGA design.

The latest release of HES-DVM provides a simulation acceleration flow that significantly speeds up RTL simulation for designs targeting Microchip FPGA devices.
Henderson, NV, USA – November 3, 2020 – Aldec, Inc. (hereinafter referred to as "Aldec"), a pioneer in HDL mixed-language simulation and hardware-assisted verification for FPGAs and ASICs, announced the HES-DVM simulation acceleration flow for Microchip Polarfire, SmartFusion2, and RTSX/RTAX FPGA designs using Aldec's HES-MPF500-M2S150 prototyping board.
Please refer to the attached document for more details.

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