HES prototyping board

Henderson, NV, USA – July 19, 2021 – Aldec, Inc. (hereinafter "Aldec"), a pioneer in HDL mixed-language simulation and hardware-assisted verification for FPGA and ASIC, has released the ASIC/SoC physical prototyping/hardware emulation board "HES-VU19PD-ZU7EV," which supports designs of approximately 83M ASIC gates. Compared to boards of the same capacity, the HES-VU19PD-ZU7EV uses only two FPGAs for logic. This facilitates FPGA partitioning and reduces the time required to launch design projects targeting mid-sized ASICs or SoCs. Additionally, for large designs, it can achieve functionality equivalent to 332M ASIC gates by connecting four boards via a high-speed backplane (scheduled for release later this year). By interconnecting the backplanes (up to three), it is also possible to support designs of approximately 996M ASIC gates. Please refer to the attached document for more details.

Henderson, NV, USA – June 2, 2021 – Aldec, Inc. (hereinafter referred to as "Aldec"), a pioneer in HDL mixed-language simulation and hardware-assisted verification for FPGA and ASIC, has released the HES-DVM Proto Cloud Edition (CE). The HES-DVM Proto CE is offered through Amazon Web Services (AWS) and can be used for FPGA-based prototyping of SoC/ASIC designs. It also focuses on automatic partitioning of designs, significantly reducing startup time when up to four FPGAs are required to accommodate the design. Please refer to the attached document for more details.

The latest release of HES-DVM provides a simulation acceleration flow that significantly speeds up RTL simulation for designs targeting Microchip FPGA devices. Henderson, NV, USA – November 3, 2020 – Aldec, Inc. (hereinafter referred to as "Aldec"), a pioneer in HDL mixed-language simulation and hardware-assisted verification for FPGAs and ASICs, announced the HES-DVM simulation acceleration flow for Microchip Polarfire, SmartFusion2, and RTSX/RTAX FPGA designs using Aldec's HES-MPF500-M2S150 prototyping board. Please refer to the attached document for more details.