BC, 2×RT, MT simultaneous operation possible MIL-STD-1553 terminal (parallel interface, SPI interface)
The 3.3V CMOS HI-613x devices provide a complete single or multifunction interface between the host processor and the MIL-STD-1553B bus. It includes BC, MT, and 2×RT, which can be enabled to operate simultaneously in any combination. Users can allocate 64KByte of on-chip SRAM to the device according to application requirements. ■ Host Interface - HI-6130: 16-Bit Parallel Bus - HI-6131: 4-Wire Serial Peripheral Interface (SPI) ■ Japanese technical documentation on the MIL-STD-1553 communication standard is available. If you would like to see it, please contact sales@nacelle.co.jp.
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basic information
■Features - BC, MT, 2×RT - Host Interface HI-6130: 16Bit Parallel Bus HI-6131: 4-Wire SPI - 64Kbyte Internal SRAM - Fully Programmable Bus Controller with 28 OP Code Instruction Set - MT records commands and data separately, adding 16Bit or 48Bit time tags - Time tags in IRIG-106 Chapter 10 format - RAM Error Detection/Correction Option - Built-in Self-Test for Protocol Logic, Digital Signal Path, and Internal RAM - Optional Self-Initialization at Reset from External Serial EEPROM - ±8kV ESD Protection (HBM, all pins) - Operating Temperature Range: -40℃ to +85℃ - Extended Operating Temperature Range: -55℃ to +125℃, optional burn-in - RoHS compliant lead-free option
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MIL-STD-1553 terminal equipment, flight control and monitoring, sensor interface, test equipment
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