Resolve issues with the actual machine early in the design phase.
The mismatch problem between simulation and logic synthesis can lead to malfunctions in physical devices. Even if it is functionally perfect in RTL simulation, there may be significant design bugs in the physical implementation. RTL linting is the only way to identify and fix the mismatch issues between simulation and logic synthesis. This paper presents typical mismatch problems from simulation to logic synthesis with simple examples. For each described issue, it will be confirmed and explained through lint checks.
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**Contents (Excerpt)** ■Introduction ■Design requirements for RTL coding implementation ■How to use synthesis attributes ■Unassigned values in combinational logic ■Incorrect use of blocking/non-blocking assignments in Verilog ■Careless use of variables in VHDL ■Comparison with unknown values ■X assignments in RTL ■Issues with traditional Verilog and new SystemVerilog constructs ・Verilog-95 sensitivity list ・SystemVerilog 2-state values ■Conclusion
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Aldec Japan, Inc. is a leading EDA tool vendor in the industry, releasing innovative design creation, simulation, verification solutions, and a variety of development boards, which are adopted for the development of large-scale FPGA/ASIC/SoC and embedded system designs. The fields we are involved in span various areas, including telecommunications, automotive, educational and research institutions, and the aerospace industry. Please feel free to contact us if you have any inquiries.
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