We have compiled a list of manufacturers, distributors, product information, reference prices, and rankings for IP Cores.
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IP Cores Product List and Ranking from 29 Manufacturers, Suppliers and Companies

Last Updated： Aggregation Period:Dec 17, 2025～Jan 13, 2026
This ranking is based on the number of page views on our site.

IP Cores Manufacturer, Suppliers and Company Rankings

Last Updated： Aggregation Period:Dec 17, 2025～Jan 13, 2026
This ranking is based on the number of page views on our site.

  1. 富士ソフト インダストリービジネス事業部 Kanagawa//software
  2. Euresys Japan ユレシス　ジャパン Kanagawa//Electronic Components and Semiconductors
  3. アローセブン Shizuoka//Industrial Machinery
  4. 4 パシフィック湘南 Kanagawa//Other manufacturing
  5. 5 デザイン・ゲートウェイ Tokyo//Electronic Components and Semiconductors
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IP Cores Product ranking

Last Updated： Aggregation Period:Dec 17, 2025～Jan 13, 2026
This ranking is based on the number of page views on our site.

  1. A system to notify when passing by to prevent forklift accidents in the factory. パシフィック湘南
  2. IP Core Catalog Euresys Japan ユレシス　ジャパン
  3. Equipment Abnormality Wireless Monitoring System アローセブン
  4. Quantum-resistant cryptographic IP core for IoT devices 富士ソフト インダストリービジネス事業部
  5. 4 CoaXPress IP Core Euresys Japan ユレシス　ジャパン

IP Cores Product List

76～90 item / All 112 items

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IP core "AndesCore A25"

IP core "AndesCore A25"

It also includes modes for low power consumption and power management, as well as a debugging interface!

The "AndesCore A25" is a 32-bit CPU IP core based on the AndeStar V5 architecture, which incorporates RISC-V technology. It achieves high performance per MHz and operates at high frequencies with a low gate count. Additionally, the Andes Custom Extension (ACE) is offered as an option to add custom instructions that lead to performance improvements and optimization of performance/power. 【Specifications (partial)】 ■ AndeStar V5 Instruction Set Architecture (ISA) utilizing RISC-V technology ■ DSP/SIMD ISA suitable for digital signal processing ■ Floating-point extension ■ Andes extension features that enable high performance and high functionality *For more details, please refer to the related links or feel free to contact us.

  • ASIC

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IP core "AndesCore D25F"

IP core "AndesCore D25F"

A flexibly configurable platform to support a wide range of system event scenarios!

The "AndesCore D25F" is a 32-bit CPU IP core based on the AndeStar V5 architecture, which incorporates RISC-V technology. For Linux-based applications, it supports the RISC-V P-extension (draft) DSP/SIMD ISA, which has been significantly contributed to by Andes Technology, as well as single-precision/double-precision floating-point instructions and an MMU. Additionally, options are available for branch prediction for efficient branch instruction execution, instruction and data caches, local memory for low-latency access, and ECC for L1 memory soft error protection. 【Specifications (partial)】 ■ AndeStar V5 Instruction Set Architecture (ISA) utilizing RISC-V technology ■ DSP/SIMD ISA suitable for digital signal processing ■ Floating-point extension ■ Andes extensions that enable high performance and high functionality *For more details, please refer to the related links or feel free to contact us.

  • ASIC

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IP core "AndesCore A25MP"

IP core "AndesCore A25MP"

Symmetric multi-processor with up to 4 cores! Supports level-2 cache and cache coherence.

The "AndesCore A25MP" is a 32-bit multi-core CPU IP core based on the AndeStar V5 architecture. It features an MMU for Linux-based applications, branch prediction for efficient branch instruction execution, level-1 instruction and data caches, and local memory for low-latency access. Additionally, it supports up to four cores and a level-2 cache controller with instruction and data prefetch. 【Specifications (partial)】 ■ Symmetric multiprocessor with up to 4 cores ■ Supports level-2 cache and cache coherence ■ AndeStar V5 Instruction Set Architecture (ISA) Compliant with RISC-V ISA IMACFDN, including Andes performance/function extensions ■ Floating-point extension *For more details, please refer to the related links or feel free to contact us.

  • ASIC

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IP core "AndesCore N9"

IP core "AndesCore N9"

Designers can set specific parameters to adjust the size, power consumption, and performance of the CPU!

The "AndesCore N9" is an IP core designed for applications that require interrupt response capabilities, such as wireless networking, sensors, microcontrollers, and automotive electronics. The low-power N9 family processor has a small gate count, low interrupt latency, and low-cost debugging. The processor family provides excellent performance and outstanding interrupt handling response while addressing the challenges of low dynamic and static power constraints. 【Specifications】 ■ High-performance V3 ISA based on a compact CPU architecture ■ Excellent overall performance ■ Efficient pipeline optimized for local memory access ■ High configurability including AXI bus support *For more details, please refer to the related links or feel free to contact us.

  • ASIC

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IP core "AndesCore N13"

IP core "AndesCore N13"

With an 8-stage pipeline and a clock frequency exceeding 1GHz, the core delivers excellent performance of 2.05 DMIPS/MHz!

The "AndesCore N13" is a high-performance CPU core designed for compute-intensive applications running on operating systems or bare metal. It is designed to meet the stringent requirements of application processors for consumer electronics such as HDTVs, home media servers, and set-top boxes, as well as the SoCs for switches and routers that deliver content to these devices. Equipped with a memory management unit, L1/L2 cache, local memory, DMA, FPU, vector interrupts, and branch prediction, it can easily run complex operating systems like Linux. 【Specifications】 ■ Optimized pipeline for best performance at 1GHz or higher ■ Dynamic branch prediction accelerates loop execution ■ ULM (Unified Local Memory) for parallel access ■ 64-bit AXI bus for high bandwidth and low latency ■ MMU and MPU for Linux and RTOS ■ Supports FPU coprocessor and L2 cache *For more details, please refer to the related links or feel free to contact us.

  • ASIC

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IP core "AndesCore N10"

IP core "AndesCore N10"

You can bridge the internet connection of ZigBee, Bluetooth, or WiFi sensor devices!

The "AndesCore N10" is an IP core suitable for applications ranging from consumer media players and smart glasses to touch panels, motor control, and power management. It features a 5-stage pipeline and operates at clock frequencies exceeding 800MHz, providing sufficient performance for automotive electronics and industrial control. Additionally, it comes with I/D cache or local memory options, allowing the core to run more efficiently in network or communication applications. 【Specifications】 ■ Cache for high-speed code and data access ■ Local memory for code and data access ■ IEEE754 compliant FPU coprocessor ■ Memory Protection Unit (MPU) for secure RTOS ■ Memory Management Unit (MMU) for Linux *For more details, please refer to the related links or feel free to contact us.

  • ASIC

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IP core "AndesCore E8"

IP core "AndesCore E8"

FlashFetch improves performance while saving power!

The "AndesCore E8" is a power-efficient and compact embedded controller enabled by the unique Andes Custom Extension (ACE). With its proprietary ACE environment, designers can specify architectural elements suitable for IoT applications. Using Andes' Custom-Optimized Instruction Development Tools (COPILOT), designers can create custom instructions that differentiate their products and designs from competing products based on standard instruction set processors. 【Specifications】 ■ Class-leading performance per MHz ■ Andes Custom Extension (ACE) significantly improves performance efficiency ■ Small footprint with fewer gates and high code density ■ Faster flash access and reduced power consumption through FlashFetch technology *For more details, please refer to the related links or feel free to contact us.

  • ASIC

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SAS Target IP Core for FPGA and ASIC

SAS Target IP Core for FPGA and ASIC

Supports SAS 3.0Gbps, 6.0Gbps, and 12.0Gbps! Equipped with automatic credit control function.

The "IP Core SAS Target for FPGA and ASIC" complies with the SAS 3.0 standard and supports a maximum transfer rate of 12Gbps (1200MB/s) for Serial-SCSI (SAS) target (device). It consists of four blocks (Phy layer, LINK layer, PORT layer, TRN layer) and interfaces with processors, SerDes, and memory. It is designed to connect to SAS-compliant host applications to transmit and receive OOB signals, primitives, and SAS frames. 【Specifications (Excerpt)】 ■ Compliant with SAS 3.0 standard ■ Supports SAS 3.0Gbps, 6.0Gbps, and 12.0Gbps ■ Register access to link layer/transport layer ■ Supports SerDes, PIPE, and SAPIS interfaces ■ Supports OOB sequence and speed negotiation sequence *For more details, please download the PDF or feel free to contact us.

  • ASIC

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Quantum-resistant cryptographic IP core for financial institutions

Quantum-resistant cryptographic IP core for financial institutions

Protecting financial transactions from the threat of quantum computers.

In the financial industry, advanced security measures are essential to protect customers' assets and confidential information. Particularly with the advent of quantum computers, the risk of traditional encryption technologies being compromised has increased. To safeguard transactions from this threat, the implementation of post-quantum cryptography is urgent. Our "Post-Quantum Cryptography IP Core" provides a hardware-level security solution that uses algorithms selected by NIST and CNSA to protect data and hardware from quantum computer attacks. 【Use Cases】 * Online banking * Credit card payments * Securities trading * Data communication between financial institutions 【Benefits of Implementation】 * Enhanced safety of customer data * Increased reliability of financial transactions * Compliance with regulations * Assurance of business continuity

  • Other Software

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[For Government] Quantum-resistant Cryptographic IP Core

[For Government] Quantum-resistant Cryptographic IP Core

Security solutions that protect data and hardware.

In government agencies, advanced security measures are essential to protect national secrets and important information assets of the citizens. The development of quantum computers poses a threat to traditional encryption technologies, increasing the risk of information leakage. Therefore, solutions that can protect data from attacks by quantum computers and ensure security are in demand. 【Use Cases】 * Protection of confidential data in government agencies * Strengthening the security of critical infrastructure * Ensuring the confidentiality of communications 【Benefits of Implementation】 * Reduction of risks associated with decryption by quantum computers * Prevention of national losses due to information leakage * Establishment of a secure information communication environment

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Quantum-resistant cryptographic IP core for healthcare

Quantum-resistant cryptographic IP core for healthcare

Hardware-level security that protects the safety of medical data.

In the healthcare industry, protecting patients' confidential information and medical data is the top priority. The advancement of quantum computers threatens traditional encryption technologies, increasing the risk of unauthorized access and data breaches for these critical data. To protect patient privacy and maintain the reliability of healthcare institutions, the implementation of quantum-resistant encryption technology is essential. 【Use Cases】 * Electronic medical record systems * Telemedicine platforms * Data management in research institutions * Communication of medical devices 【Benefits of Implementation】 * Protection of data from attacks by quantum computers * Maintenance of patient data confidentiality * Strengthening the security of medical information systems * Compliance with regulations

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Quantum-resistant cryptographic IP core for smart grids

Quantum-resistant cryptographic IP core for smart grids

Security solutions to protect the data and hardware of smart grids.

In the smart grid industry, ensuring the stability and security of power supply is essential. Particularly, with the advancement of quantum computers, the risk of traditional encryption methods being compromised is increasing. This raises the possibility of unauthorized access to control data of power systems and customer information, which could have serious implications for the entire social infrastructure. Our "Post-Quantum Cryptography IP Core" utilizes algorithms selected by NIST and CNSA to protect data and hardware from quantum computer attacks, thereby supporting the secure operation of smart grids. 【Use Cases】 * Smart meters * Power control systems * Data communication in transmission networks 【Benefits of Implementation】 * Protection from attacks by quantum computers * Improved reliability of power systems * Maintenance of confidentiality for critical data

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