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IP Cores Product List and Ranking from 29 Manufacturers, Suppliers and Companies

Last Updated： Aggregation Period:Dec 17, 2025～Jan 13, 2026
This ranking is based on the number of page views on our site.

IP Cores Manufacturer, Suppliers and Company Rankings

Last Updated： Aggregation Period:Dec 17, 2025～Jan 13, 2026
This ranking is based on the number of page views on our site.

  1. 富士ソフト インダストリービジネス事業部 Kanagawa//software
  2. Euresys Japan ユレシス　ジャパン Kanagawa//Electronic Components and Semiconductors
  3. アローセブン Shizuoka//Industrial Machinery
  4. 4 パシフィック湘南 Kanagawa//Other manufacturing
  5. 5 デザイン・ゲートウェイ Tokyo//Electronic Components and Semiconductors
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IP Cores Product ranking

Last Updated： Aggregation Period:Dec 17, 2025～Jan 13, 2026
This ranking is based on the number of page views on our site.

  1. A system to notify when passing by to prevent forklift accidents in the factory. パシフィック湘南
  2. IP Core Catalog Euresys Japan ユレシス　ジャパン
  3. Equipment Abnormality Wireless Monitoring System アローセブン
  4. Quantum-resistant cryptographic IP core for IoT devices 富士ソフト インダストリービジネス事業部
  5. 4 CoaXPress IP Core Euresys Japan ユレシス　ジャパン

IP Cores Product List

91～105 item / All 112 items

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Military-grade quantum-resistant cryptographic IP core

Military-grade quantum-resistant cryptographic IP core

Security solutions that protect data and hardware.

In the military field, the protection of confidential information and secure communication are essential. The advancement of quantum computers poses a threat to traditional encryption technologies, making the introduction of quantum-resistant cryptographic techniques an urgent necessity to prevent data leaks and unauthorized access. This product provides a hardware-level security solution that uses algorithms selected by NIST and CNSA to protect data and hardware from attacks by quantum computers. 【Use Cases】 - Encryption of highly confidential communications - Protection of important data - Strengthening the security of military systems 【Benefits of Implementation】 - Reduction of risks associated with decryption by quantum computers - Maintenance of data confidentiality - Improvement of system security levels

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Quantum-resistant cryptographic IP core for IoT devices

Quantum-resistant cryptographic IP core for IoT devices

Hardware-level solutions to enhance the security of IoT devices.

In the field of IoT device authentication, secure identification of devices and protection of data are essential. With the advancement of quantum computers, traditional encryption methods are under threat, increasing the security risks for IoT devices. This product uses algorithms selected by NIST and CNSA to protect devices and data from quantum computer attacks. 【Use Cases】 - Authentication of IoT devices - Secure data communication - Protection of firmware 【Benefits of Implementation】 - Prevention of device impersonation - Maintenance of data confidentiality - Assurance of long-term security

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[For Educational Institutions] Quantum-Resistant Cryptography IP Core

[For Educational Institutions] Quantum-Resistant Cryptography IP Core

Hardware-level security solutions to enhance the safety of online exams.

In online examinations at educational institutions, the confidentiality of exam data and the protection of candidates' privacy are essential. With the advancement of quantum computers, the risk of traditional encryption methods being compromised is increasing, making it urgent to implement measures to prevent unauthorized access to and tampering with exam results. Our quantum-resistant cryptographic IP core adopts algorithms selected by NIST and CNSA, protecting exam data and hardware from attacks by quantum computers. 【Use Cases】 - Online exam platforms - Encryption and decryption of exam data - Measures against unauthorized access 【Benefits of Implementation】 - Secure protection of exam data - Deterrence of cheating - Establishment of a reliable exam environment

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DapTechnology FireLink LLC IP Core

DapTechnology FireLink LLC IP Core

FireLink is a link layer controller IP core compliant with IEEE-1394b.

FireLink, a synthesizable IEEE-1394-2008 beta link layer controller (LLC) core, is based on the link layer controller that has been used in DapTechnology's FireSpy analyzer products for several years. FireLink is a mature core implemented on FPGAs from Xilinx, Altera, and Microsemi. FireLink is available in three configurations: Basic, Extended, and GPLink. ■Japanese technical documentation for AS5643 is available. If you would like to see it, please contact sales@nacelle.co.jp■

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TOE1G-IP core for FPGA

TOE1G-IP core for FPGA

You can implement TCP/IP communication functionality with pure hardware logic without a CPU!

The TCP Offloading Engine IP Core (TOE1G-IP) is a groundbreaking solution that enables the complex TCP transmission and reception processes, which traditionally required expensive high-end CPUs, to be implemented solely with pure hardware logic without a CPU. It comes standard with a reference design compatible with Xilinx/Altera FPGAs, which can help shorten product development time.

  • ASIC

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IP core "AndesCore NX25F"

IP core "AndesCore NX25F"

Optimized for high operating frequency and high performance! Supports single-precision/double-precision floating-point instructions.

The "AndesCore NX25F" is a compact 64-bit CPU IP core based on the AndeStar V5 architecture, which incorporates RISC-V technology. It is optimized for high-performance embedded applications that require access to an address space exceeding 4GB. Additionally, Andes Custom Extension (ACE) is offered as an option to add custom instructions that lead to performance improvements and optimization of performance/power. 【Specifications (partial)】 ■ AndeStar V5 Instruction Set Architecture (ISA) utilizing RISC-V technology ■ Floating-point extension ■ Andes extensions capable of achieving high performance and high functionality ■ Andes Custom Extension (ACE) available under separate licensing for customization and custom instructions *For more details, please refer to the related links or feel free to contact us.

  • ASIC

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IP core "AndesCore N25F"

IP core "AndesCore N25F"

High code density 16/32-bit mixed instruction format!

The "AndesCore N25F" is a 32-bit CPU IP core based on the AndeStar V5 architecture, which incorporates RISC-V technology. It achieves high performance per MHz and operates at high frequencies with a low gate count, supporting single-precision and double-precision floating-point instructions. Additionally, the Andes Custom Extension (ACE) is offered as an option to add custom instructions that lead to performance improvements and optimization of performance/power. 【Specifications (partial)】 ■ AndeStar V5 Instruction Set Architecture (ISA) utilizing RISC-V technology ■ Floating-point extension ■ Andes extensions capable of achieving high performance and high functionality ■ Andes Custom Extension (ACE) available for separate licensing for customization and custom instructions *For more details, please refer to the related links or feel free to contact us.

  • ASIC

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IP core "AndesCore N22"

IP core "AndesCore N22"

There are configurable settings that allow for trade-offs between core size and performance requirements!

The "AndesCore N22" is a 32-bit, dual-stage pipeline CPU IP core based on the AndeStar V5 architecture, designed for embedded applications that require low power consumption and small circuit size. It complies with RISC-V technology and features several efficient performance capabilities, including simple dynamic branch prediction, instruction cache, and local memory. Additionally, it comes with a rich set of optional features such as a JTAG debug interface for development support. 【Specifications (partial)】 ■ AndeStar V5/V5e Instruction Set Architecture (ISA) based on RISC-V technology ■ Supports RV32IMAC/EMAC ■ Andes extensions that enable high performance and high functionality ■ 32-bit, dual-stage pipeline CPU architecture ■ High code density with mixed 16/32-bit instruction formats *For more details, please refer to the related links or feel free to contact us.

  • ASIC

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IP core "AndesCore AX25MP"

IP core "AndesCore AX25MP"

64-bit CPU architecture! It can access an address space significantly exceeding 4GB.

The "AndesCore AX25MP" is a 64-bit multi-core CPU IP core based on the AndeStar V5 architecture. It features an MMU for Linux-based applications, branch prediction for efficient branch instruction execution, level-1 instruction and data caches, and local memory for low-latency access. Additionally, it supports up to 4 cores and a level-2 cache controller with instruction and data prefetch. 【Specifications (partial)】 ■ Symmetric multiprocessor with up to 4 cores ■ Supports level-2 cache and cache coherence ■ AndeStar V5 Instruction Set Architecture (ISA) Compliant with RISC-V ISA IMACFDN, including Andes performance/function extensions ■ Floating-point extension *For more details, please refer to the related links or feel free to contact us.

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IP core "AndesCore N15/N15F"

IP core "AndesCore N15/N15F"

It is equipped with an IEEE-754 compliant floating-point unit that enhances floating-point processing capabilities!

The "AndesCore N15/N15F" is a dual-issue superscalar AndesCore processor. It offers a performance of 5.41 CoreMark/MHz and comes with various configuration options such as MMU, cache, and local memory. Additionally, the 64-bit data bus for cache, local memory, and main bus provides the bandwidth necessary for instruction fetch and data access. 【Specifications】 ■ Dual-issue pipeline ■ Cache for fast code and data access ■ Local memory for code and data access ■ Built-in IEEE754 compliant FPU coprocessor (N15F) ■ Memory Management Unit (MMU) for Linum ■ 64-bit AXI4/AHB/AHBx2 bus interface *For more details, please refer to the related links or feel free to contact us.

  • ASIC

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IP core "AndesCore D15/D15F"

IP core "AndesCore D15/D15F"

It comes with various configuration options such as MMU, cache, and local memory!

The "AndesCore D15/D15F" is a dual-issue superscalar AndesCore processor. Both processors are equipped with over 130 compiler-friendly general-purpose DSP and SIMD instructions to easily program DSP algorithms in C/C++. They are also designed for a variety of performance-driven applications in embedded Linux, real-time OS, or bare-metal environments. 【Specifications (partial)】 ■ Dual-issue pipeline ■ Over 130 DSP extension instructions ■ Cache for fast code and data access ■ Local memory for code and data access ■ Built-in IEEE754 compliant FPU coprocessor (D15F) *For more details, please refer to the related links or feel free to contact us.

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IP core "AndesCore N7"

IP core "AndesCore N7"

It is possible to reduce it to 12K gates! It serves as an ideal alternative to the 8051 and other 8-bit processor cores.

The "AndesCore N7" is an IP core that supports controllers requiring low power consumption, such as touch screens, storage, mobile devices, and sensors, as well as network connectivity needed for IoT devices. The ultra-low power consumption and small circuit size of the N7 are designed for SOC designs with performance constraints. FlashFetch technology can enhance the performance of latency-prone flash memory without additional power consumption. 【Specifications】 ■ Seamless transition from 8/16-bit MCUs to a complete 32-bit environment ■ Low power consumption to extend battery life ■ Small footprint with fewer gates and high code density ■ Speeding up Flash access and reducing power consumption with FlashFetch technology *For more details, please refer to the related links or feel free to contact us.

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IP core "AndesCore D10"

IP core "AndesCore D10"

The optimized DSP library and C/C++ compiler make programming algorithms easier!

The "AndesCore D10" is a 5-stage pipeline integer processor equipped with a DSP that includes 130 DSP SIMD (Single Instruction, Multiple Data) instructions. Targeting the real-time processing requirements of multimedia applications with power constraints, the D1088 achieves 588 DMIPS using a 90nm low-power process. Additionally, for voice applications, the D1088 provides left shift, right rounding and shift, most significant word, 32x32 multiplication, and specially designed 32-bit instructions to replace long 64-bit calculations. 【Specifications】 ■ Over 130 DSP extended instructions ■ Cache for fast code and data access ■ Local memory for code and data access ■ Built-in IEEE754 compliant FPU coprocessor ■ Memory Protection Unit (MPU) for RTOS ■ Memory Management Unit (MMU) for Linum *For more details, please refer to the related links or feel free to contact us.

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IP core "AndesCore S8"

IP core "AndesCore S8"

A secure MPU against memory tampering! It is equipped with a shield against side-channel attacks.

The "AndesCore S8" is an IP core based on the N8 core computing engine, with added features to address security against hacking. The secure memory protection unit (MPU: Memory Protection Unit) at the center strictly protects execution and access according to multiple security levels. Additionally, it includes defenses against hacking targeting the interface between the CPU and memory, as well as the capability to monitor the CPU's power usage signature to prevent program hacking. 【Specifications】 ■ Secure MPU against memory tampering ■ Shield against side-channel attacks ■ Secure debugging for multi-party software development ■ Flexible configuration and runtime control *For more details, please refer to the related links or feel free to contact us.

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