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  6. Test chip with next-generation solder bumps

Test chip with next-generation solder bumps

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JTEG Phase10

last updated:Jun 17, 2011

ウェル
ウェル
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Test chip with next-generation solder bumps.

Next-generation test chip with Low-K film used in the interlayer dielectric layer for solder bumps ■Wafer size: 8-inch wafer ■Base chip size: 5.02mm × 5.02mm ■Pad pitch: 200μm (staggered pads) ■Number of pads: 484 bumps ■Compatible bump processes: Eutectic solder / Lead-free solder ■Compatible substrate: JKIT Type 5 ■Options: Bump mounting / Dicing processing / Back grinding processing / Surface polyimide film formation ■Main applications: Package development, process ramp-up / Development, promotional data acquisition, etc.

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Test chip with next-generation solder bumps

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  • Related Link - http://well-teg.jp/

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basic information

The JTEG and JKIT from Hitachi Ultra LSI Systems, which we are introducing here, ceased production of all products as of December 2009. The latest information on Well's original open TEG chip "JCHIP" can be found here: http://well-teg.jp/

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Our test chips are standard TEG chips developed to accommodate various methods for SIP development, PKG development, implementation method development, PCB substrate development, implementation and inspection equipment development, and material development applications, and are already used by over 200 customers both domestically and internationally. We also accept orders for custom chips with special specifications.

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Electronic Components and Semiconductors

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Well develops and implements a packaging solution business centered on test chips for advanced implementation evaluation, covering everything from bare chip packaging equipment development and contract implementation to reliability evaluation. ~ Corporate Philosophy ~ ■ With "Profitable Relationship" as the core of our management philosophy, we aim to be a company that contributes to the prosperity of our customers and the development of the globally expanding electronics components industry. ■ Through the provision of products that support next-generation semiconductor packaging development, we contribute to the promotion of our customers' development and the enhancement of their profits. ■ We aim to create valuable markets by providing "innovative products" and "cutting-edge services."

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