To achieve a design that is not affected by metastability.
Clock Domain Crossing (CDC) issues are causing significant failures in ASIC and FPGA devices. As the complexity and performance of FPGAs increase, the impact of CDC issues on design functionality becomes even greater. This paper discusses CDC issues and solutions for FPGA design. It presents various design techniques along with examples from Xilinx and Intel FPGA devices. More importantly, this paper summarizes the most critical CDC guidelines for reliable FPGA design.
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**Contents (Excerpt)** ■ The impact of metastability ■ Two flip-flop synchronizer as a general CDC solution ■ Implementation of a safe synchronizer in FPGA ・ Half-cycle synchronizer in FPGA ・ Functional non-determinism of CDC signals ■ Data synchronizer ・ Control-based data synchronizer ・ FIFO-based data synchronizer ・ Implementation of data synchronizer in FPGA ■ Reset synchronizer in FPGA ■ Cross-domain clocking techniques for high-reliability FPGA devices
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Aldec Japan, Inc. is a leading EDA tool vendor in the industry, releasing innovative design creation, simulation, verification solutions, and a variety of development boards, which are adopted for the development of large-scale FPGA/ASIC/SoC and embedded system designs. The fields we are involved in span various areas, including telecommunications, automotive, educational and research institutions, and the aerospace industry. Please feel free to contact us if you have any inquiries.