A platform capable of achieving DO-254/ED-80 verification objectives in a test environment using a target board.
DO-254/CTS is a hardware and software platform customized to reinforce testing by the target board, enhance verification coverage, and achieve the verification objectives of DO-254/ED-80. The target design runs at real speed on the target device with a custom daughter card. It uses a simulation test bench as test vectors, performing requirement-based verification while maintaining 100% control and monitoring at the FPGA pin level, allowing for testing in both normal and abnormal ranges. FPGA test results can be captured at real speed and displayed in the simulator's waveform viewer for advanced analysis and documentation.
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basic information
- At-speed testing on target devices - Reuse test benches as test vectors - Improve verification coverage through testing - Visualize and control all FPGA I/O - Easy access to FPGA hardware boards for device testing - Support for FPGA devices from Intel (Altera), Lattice, Microsemi, and Xilinx - Support for high-speed serial I/O on FPGA (ARINC 818, PCIe, DDR3, and LVDS) - A single environment capable of verifying all FPGA-level requirements - Automated in-hardware testing - Visualize hardware test results with a waveform viewer - Integration with third-party RTL simulators, synthesis tools, and place-and-route tools
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Applications/Examples of results
Achievement of DO-254/ED-80 verification objectives.
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Company information
Aldec Japan, Inc. is a leading EDA tool vendor in the industry, releasing innovative design creation, simulation, verification solutions, and a variety of development boards, which are adopted for the development of large-scale FPGA/ASIC/SoC and embedded system designs. The fields we are involved in span various areas, including telecommunications, automotive, educational and research institutions, and the aerospace industry. Please feel free to contact us if you have any inquiries.
![Introduction to our achievements in building UVM-based verification environments [Document available]](https://image.mono.ipros.com/public/product/image/400641/IPROS5112791923415090604.png?w=280&h=280)