We have compiled a list of manufacturers, distributors, product information, reference prices, and rankings for core.
ipros is IPROS GMS ・ IPROS One of the largest technical database sites in Japan that collects information on.

core(CPU) - List of Manufacturers, Suppliers, Companies and Products

Last Updated： Aggregation Period:Sep 17, 2025～Oct 14, 2025
This ranking is based on the number of page views on our site.

core Product List

1～15 item / All 27 items

Displayed results
TOE100G-IP core for FPGA

TOE100G-IP core for FPGA

Achieving 100G TCP/IP communication functionality with pure hardware logic without CPU!

The 100GbE TCP Offloading Engine IP Core (TOE100G-IP) is a groundbreaking solution that enables the implementation of complex TCP transmission and reception processes, which traditionally required expensive high-end CPUs, using only pure hardware logic without a CPU. It comes standard with a reference design compatible with Xilinx/Intel FPGAs, which can help shorten product development time.

  • ASIC

Added to bookmarks

Bookmarks list

Bookmark has been removed

Bookmarks list

You can't add any more bookmarks

By registering as a member, you can increase the number of bookmarks you can save and organize them with labels.

Free membership registration
TOE10G-IP core for FPGA

TOE10G-IP core for FPGA

Achieving 10 times faster 10GbE TCP/IP communication functionality with pure hardware logic without CPU!

The 10GbE TCP Offloading Engine IP Core (TOE10G-IP) is a groundbreaking solution that allows complex TCP transmission and reception processing, which traditionally required expensive high-end CPUs, to be implemented solely with pure hardware logic without a CPU. It comes standard with a reference design compatible with Xilinx/Intel FPGAs, which can help shorten product development time.

  • ASIC

Added to bookmarks

Bookmarks list

Bookmark has been removed

Bookmarks list

You can't add any more bookmarks

By registering as a member, you can increase the number of bookmarks you can save and organize them with labels.

Free membership registration
TOE40G-IP core for FPGA

TOE40G-IP core for FPGA

Achieving 40 times speed 10GbE TCP/IP communication functionality with pure hardware logic without CPU!

The 40GbE TCP Offloading Engine IP Core (TOE40G-IP) is a groundbreaking solution that enables the complex TCP transmission and reception processes, which traditionally required expensive high-end CPUs, to be implemented solely with pure hardware logic without a CPU. It comes standard with a reference design compatible with Xilinx/Intel FPGAs, which can help shorten product development time.

  • ASIC

Added to bookmarks

Bookmarks list

Bookmark has been removed

Bookmarks list

You can't add any more bookmarks

By registering as a member, you can increase the number of bookmarks you can save and organize them with labels.

Free membership registration
NVMe IP core for FPGA

NVMe IP core for FPGA

Supports PCIe Gen4 SSD, no external memory required, 2ch RAID0, compatible with random access.

The NVMe IP core is an IP core that interfaces next-generation storage PCIe SSDs, which serve as a replacement for SATA SSDs, with FPGAs without the need for a CPU or external memory. A reference design that operates on various Xilinx/Intel FPGA evaluation boards is included as standard, allowing development to start based on this reference design, enabling rapid product development. This NVMe IP core maximizes the performance of NVMe PCIe SSDs, achieving high-speed transfers of over 3300MB/s (evaluated with KCU105 and Samsung 970 Pro). Time-limited bit/sof files for various Xilinx/Intel FPGA boards are prepared, allowing performance evaluation on actual hardware before purchase.

  • ASIC

Added to bookmarks

Bookmarks list

Bookmark has been removed

Bookmarks list

You can't add any more bookmarks

By registering as a member, you can increase the number of bookmarks you can save and organize them with labels.

Free membership registration
25G TOE IP core for FPGA

25G TOE IP core for FPGA

Achieving 25G TCP/IP communication functionality with pure hardware logic without CPU!

The 25GbE TCP Offloading Engine IP Core (TOE25G-IP) is a groundbreaking solution that enables the complex TCP transmission and reception processes, which traditionally required expensive high-end CPUs, to be implemented solely with pure hardware logic without a CPU. It comes standard with a reference design compatible with Xilinx/Intel FPGAs, which can help shorten product development time. It provides 25G performance and bandwidth, which is 2.5 times that of the conventional 10G in a single channel. This significantly reduces power consumption and cost per gigabit.

  • ASIC

Added to bookmarks

Bookmarks list

Bookmark has been removed

Bookmarks list

You can't add any more bookmarks

By registering as a member, you can increase the number of bookmarks you can save and organize them with labels.

Free membership registration
Sprite Drawing IP Core (Verilog)

Sprite Drawing IP Core (Verilog)

Sprite Drawing IP Core (Verilog)

This process overlays character images (sprites) onto a background image. The maximum image size is 1024x1024. Arbitrary angle rotation in 0.35-degree increments. During rotation, a bi-linear interpolated image is created. Mirror flipping. Alpha blending. The maximum number of overlays is 16.

  • Other semiconductors

Added to bookmarks

Bookmarks list

Bookmark has been removed

Bookmarks list

You can't add any more bookmarks

By registering as a member, you can increase the number of bookmarks you can save and organize them with labels.

Free membership registration
UDP 10G IP Core for FPGA

UDP 10G IP Core for FPGA

Achieving 10Gbps UDP communication functionality with pure hardware logic without CPU!

The 【UDP10G IP Core】 is a groundbreaking solution that allows UDP transmission and reception processing to be implemented solely with pure hardware logic, without the need for a CPU. It also supports high-speed simultaneous transmission and reception. This can help shorten the development time for network application products that require broadcasting and low latency. Additionally, we have prepared demo files for Xilinx/Intel FPGA evaluation boards, allowing you to evaluate and test this core on actual hardware before purchase.

  • ASIC

Added to bookmarks

Bookmarks list

Bookmark has been removed

Bookmarks list

You can't add any more bookmarks

By registering as a member, you can increase the number of bookmarks you can save and organize them with labels.

Free membership registration
IP core "AndesCore AX25"

IP core "AndesCore AX25"

64-bit CPU architecture! It can access an address space significantly exceeding 4GB.

The "AndesCore AX25" is a compact 64-bit CPU IP core based on the AndeStar V5 architecture, which incorporates RISC-V technology. It is optimized for high-performance embedded applications that require access to an address space exceeding 4GB. Options such as branch prediction for efficient branch instruction execution, instruction and data caches, local memory for low-latency access, and ECC for L1 memory soft error protection are available. 【Specifications (partial)】 ■ AndeStar V5 Instruction Set Architecture (ISA) utilizing RISC-V technology ■ DSP/SIMD ISA suitable for digital signal processing ■ Floating-point extension ■ Andes extensions that enable high performance and high functionality *For more details, please refer to the related links or feel free to contact us.

  • ASIC

Added to bookmarks

Bookmarks list

Bookmark has been removed

Bookmarks list

You can't add any more bookmarks

By registering as a member, you can increase the number of bookmarks you can save and organize them with labels.

Free membership registration
IEEE1588-2008 PTP Time Synchronization IP Core

IEEE1588-2008 PTP Time Synchronization IP Core

Providing IEEE1588-2008 PTP time synchronization solutions as an IP core. Synchronizing devices on Ethernet (LAN) with nanosecond precision.

Oregano Systems offers timing synchronization solutions compliant with IEEE1588-2008 Precision Time Protocol as IP CORE. It provides syn1588 Clock_S for serial connection to external CPUs and syn1588 Clock_M for parallel connection, available in netlist or source code. Synchronization in the nanosecond range over Ethernet is possible. Support for 802.1AS will be available starting summer 2016.

  • syn1588 Clock_M GMII.jpg
  • LAN construction and wiring work

Added to bookmarks

Bookmarks list

Bookmark has been removed

Bookmarks list

You can't add any more bookmarks

By registering as a member, you can increase the number of bookmarks you can save and organize them with labels.

Free membership registration
JPEG Stretch P Core (Verilog)

JPEG Stretch P Core (Verilog)

JPEG Stretch P Core (Verilog)

JPEG Decode Verilog-HDL IP Core YUV Formats: 4:2:0 4:2:2 4:4:4 Processing Markers: SOI, APP, DQT, DHT, SOF0, SOS, EOI All others will be ignored Output Format: RGB 8:8:8 Huffman Codes: Generated from header information Quantization Table: Generated from header information

  • Other electronic parts

Added to bookmarks

Bookmarks list

Bookmark has been removed

Bookmarks list

You can't add any more bookmarks

By registering as a member, you can increase the number of bookmarks you can save and organize them with labels.

Free membership registration
Digital Simple Radio Transmitter "TFT405DA Model/TFR400DB Model"

Digital Simple Radio Transmitter "TFT405DA Model/TFR400DB Model"

Stable RTK-GNSS surveying is possible! Dustproof and rainproof structure compliant with IP45 for outdoor installation.

The "TFT405DA/TFR400DB" is a digital simple wireless transmitter that achieves an effective communication speed of 9600 bps. It adopts the π/4 shift QPSK modulation method and boasts one of the fastest communication speeds among digital simple wireless devices, specifically designed for data transmission. It is suitable for GPS-equipped surveying instruments, telemetry, and long-distance data transmission, with an interface that outputs and inputs at RS232C levels, making it easy to connect with external devices. 【Features】 - Achieves low power consumption with a general-purpose single-chip CPU configuration through a uniquely developed algorithm. - A license application is required to establish a simple wireless station (no radio operator qualification is necessary). - Suitable for RTK-GPS surveying instruments, telemetry, and long-distance data transmission. - Utilizes a one-touch metal connector for the connection part. - Complies with IP45 for dust and rain resistance, allowing for outdoor installation as is. *For more details, please refer to the PDF document or feel free to contact us.

  • Communications

Added to bookmarks

Bookmarks list

Bookmark has been removed

Bookmarks list

You can't add any more bookmarks

By registering as a member, you can increase the number of bookmarks you can save and organize them with labels.

Free membership registration
SATA IP core for FPGA

SATA IP core for FPGA

High-performance, high-reliability IP core proven by NASA (National Aeronautics and Space Administration).

The Serial ATA (SATA) IP core complies with Serial ATA Revision 3.0 and is designed to operate on FPGA devices such as Xilinx UltraScale, 7 Series, and Intel 10 Series. This IP core provides only the link layer, but reference designs for the transport layer and physical layer are available, allowing connection to SATA3 hard disks without a PHY chip. This SATA IP core maximizes the performance of SSDs, enabling high-speed transfers exceeding 500MB/s per channel. Limited-time evaluation demo files for various FPGA boards are prepared, allowing performance evaluation on actual hardware before purchase. Additionally, the core product comes standard with reference designs that operate on various Xilinx/Intel FPGA evaluation boards, enabling development to start based on this reference design, which allows for rapid product development.

  • ASIC

Added to bookmarks

Bookmarks list

Bookmark has been removed

Bookmarks list

You can't add any more bookmarks

By registering as a member, you can increase the number of bookmarks you can save and organize them with labels.

Free membership registration
Movable single-core 'OLFLEX CHAIN 90 CP'

Movable single-core 'OLFLEX CHAIN 90 CP'

UL AWM certification, made of PUR, suitable for dynamic movement! Equipped with a shield to protect against electromagnetic interference.

"OLFLEX CHAIN 90 CP" is a highly flexible, shielded power cable for moving applications. It enables significant acceleration and speed improvements, enhancing the economic efficiency of machinery. The copper shield complies with EMC requirements, protecting the cable from electromagnetic interference. 【Features】 ■ Flame retardant ■ Excellent weather resistance, UV resistance, and oil resistance ■ Maintains flexibility even at low temperatures ■ Low capacitance design ■ EMC compliant *For more details, please refer to the PDF document or feel free to contact us.

  • cable

Added to bookmarks

Bookmarks list

Bookmark has been removed

Bookmarks list

You can't add any more bookmarks

By registering as a member, you can increase the number of bookmarks you can save and organize them with labels.

Free membership registration
TOE1G-IP core for FPGA

TOE1G-IP core for FPGA

You can implement TCP/IP communication functionality with pure hardware logic without a CPU!

The TCP Offloading Engine IP Core (TOE1G-IP) is a groundbreaking solution that enables the complex TCP transmission and reception processes, which traditionally required expensive high-end CPUs, to be implemented solely with pure hardware logic without a CPU. It comes standard with a reference design compatible with Xilinx/Altera FPGAs, which can help shorten product development time.

  • ASIC

Added to bookmarks

Bookmarks list

Bookmark has been removed

Bookmarks list

You can't add any more bookmarks

By registering as a member, you can increase the number of bookmarks you can save and organize them with labels.

Free membership registration

Search Keywords Related to core

COPYRIGHT © 2001-2025 IPROS CORPORATION ALL RIGHTS RESERVED.