High connection reliability electroless copper plating process for semiconductor package substrates

basic information

With the high performance, miniaturization, and lightweight nature of electronic devices, semiconductor package substrates are becoming increasingly dense. As a result, printed circuit boards used in semiconductor packages are advancing in circuit miniaturization, reducing via hole diameters, and thinning inner layer copper. In via holes, there are three types of copper: inner layer copper, electroless copper plating, and electrolytic copper plating, viewed from the bottom. In conventional methods, as miniaturization progresses, delamination occurs at the interface between the inner layer copper and the electroless copper plating, leading to a decrease in connection reliability. The "OPC FLET process" can form a copper seed layer with excellent coverage and electrical conductivity at a low film thickness. Furthermore, it demonstrates excellent adhesion to low roughness materials. Additionally, by reducing the thickness of the electroless copper plating film, it significantly improves the circuit thinning that occurs during the etching of electroless copper plating, enabling the formation of ultra-fine wiring with L/S=5/5μm or less. Moreover, we are also focusing on the development of technologies that respond to new materials such as plating chemicals and processes for semiconductor package substrates and semiconductor packaging substrates, as well as low roughness insulating materials. If you have any concerns regarding surface treatment of printed circuit boards and electronic components, please feel free to consult us.

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Semiconductor package plating Semiconductor package substrate plating Semiconductor package substrate manufacturing Semiconductor package substrate plating process Semiconductor packaging substrate manufacturing IC substrate manufacturing IC substrate plating process