7/3 Webinar on Backend Processes, Assembly, and Design in Semiconductor Manufacturing
A systematic explanation from the basics of semiconductor backend processes and packaging technology to 2.5D/3D packaging and chiplet technology.
■Title "Fundamentals of Backend Processes, Packaging, and Design in Semiconductor Manufacturing" This seminar provides a systematic learning experience about backend processes and packaging technologies that support the high performance and functionality of semiconductors, covering everything from the basics to the latest trends. Experienced instructors will clearly explain the history of semiconductor package evolution, various package types, packaging processes, encapsulation technologies, and evaluation and analysis techniques. Additionally, the latest trends in advanced packaging technologies such as 2.5D/3D packaging, CoWoS, chiplets, hybrid bonding, and optoelectronic integration technologies that support the AI era will also be introduced. This content is recommended for engineers and researchers in fields such as chemistry, electronic components, and the automotive industry, as well as anyone who wants to learn semiconductor packaging technology from the ground up.
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basic information
■Seminar Title Fundamentals of Backend Processes, Packaging, and Design in Semiconductor Manufacturing ■Event Details Date and Time: July 3, 2026 (Friday) 13:30 - 16:30 Instructor: Yosuke Hirumuta (Hirumuta Engineering Office, Quality and Technology Consultant) Participation Fee: 44,000 yen (tax included) Newsletter Member Price: 39,600 yen (tax included) Delivery Format: Live streaming via Zoom ■Main Content - Basics and evolution of semiconductor packaging - Packaging processes and manufacturing steps - Encapsulation technology, evaluation, and analysis techniques - Key points for improving quality and reliability - Compliance with RoHS, PFAS, and sustainability - 2.5D/3D packaging and chiplets - Latest trends in CoWoS and optoelectronic integration technology - Future prospects of packaging technology in the AI era
Price information
Tuition fee: 44,000 yen (tax included) *Includes materials *Price for our newsletter subscribers (registration is free): 39,600 yen (tax included) 【Newsletter Subscriber Benefits】 If two or more people apply at the same time and all applicants are registered newsletter subscribers, the participation fee per person will be half of the newsletter subscriber price.
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Applications/Examples of results
- Basic education in semiconductor back-end processes and assembly technology - Training for semiconductor package development engineers - Technical training for electronic components and materials manufacturers - Acquisition of quality and reliability evaluation techniques - Information gathering on advanced package technologies - Understanding of semiconductor assembly technology for AI applications *For details about the program and application methods, please check the related link URL.*
Company information
We provide the latest industrial insights to our clients. By conducting market trend analysis, publishing technology‑related books and research reports, and organizing and managing seminars, we support research and development across a wide range of industries, with a primary focus on manufacturing. Our coverage spans diverse fields such as energy, batteries, chemicals, and biotechnology.
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