List of ASIC products
- classification：ASIC
91～105 item / All 139 items
Reduce the workload from handling heavy objects! Here are five case studies that solved customer challenges! We are also accepting free consultations and tests tailored to your work!
- Other conveying machines
Strong cold wind from room temperature to -13°C! Depending on the usage environment, you can choose between the combo type or the separate type!
- Cooling system
April 10, 2024 (Wednesday) to April 12, 2024 (Friday) Notice of Participation in Nagoya Manufacturing World 2024
Sanwa Shiki Ventilator Co., Ltd. will be exhibiting at the 2024 Monozukuri World (Nagoya) held at Port Messe Nagoya. We will also be showcasing our large cooling fans and cool/warm ambient products. Date: April 10, 2024 - April 12, 2024 Opening: 10:00 AM Location: Nagoya Port Messe (Exhibition Hall 1) *Our booth: 19-1 We would be grateful if you could visit us if you have the time.
NXP i.MX8M Plus equipped with Toradex's Verdin family CPU module.
- Microcomputer
- ASIC
A prototyping board equipped with two of the largest Virtex UltraScale+ and one Zynq UltraScale+.
- ASIC
A new HES board ideal for prototyping and emulation of medium to large-scale ASIC/SoC designs.
Henderson, NV, USA – July 19, 2021 – Aldec, Inc. (hereinafter "Aldec"), a pioneer in HDL mixed-language simulation and hardware-assisted verification for FPGA and ASIC, has released the ASIC/SoC physical prototyping/hardware emulation board "HES-VU19PD-ZU7EV," which supports designs of approximately 83M ASIC gates. Compared to boards of the same capacity, the HES-VU19PD-ZU7EV uses only two FPGAs for logic. This facilitates FPGA partitioning and reduces the time required to launch design projects targeting mid-sized ASICs or SoCs. Additionally, for large designs, it can achieve functionality equivalent to 332M ASIC gates by connecting four boards via a high-speed backplane (scheduled for release later this year). By interconnecting the backplanes (up to three), it is also possible to support designs of approximately 996M ASIC gates. Please refer to the attached document for more details.
We will propose an FPGA design suitable for your product!
- Circuit board design and manufacturing
- Other contract services
- ASIC
Achieving 100G TCP/IP communication functionality with pure hardware logic without CPU!
- ASIC
Supports PCIe Gen4 SSD, no external memory required, 2ch RAID0, compatible with random access.
- ASIC
Achieving 25G TCP/IP communication functionality with pure hardware logic without CPU!
- ASIC
Resolve issues with the actual machine early in the design phase.
- ASIC
Resolution of reset-related issues in ASIC and FPGA design.
- ASIC
Small board 'TySOM-1' equipped with Zynq-7000 (Z-7030) and various interfaces.
- ASIC
- Embedded Board Computers
A platform capable of achieving DO-254/ED-80 verification objectives in a test environment using a target board.
- Other semiconductors
- ASIC
Free Webinar: DO-254 FPGA Level In-Target Testing
Section 6.2 "Verification Process" of RTCA/DO-254 stipulates the need to maintain and verify requirements from the RTL simulation stage to the hardware verification stage. This regulation makes it a very important task to conduct functional verification of digital designs on actual hardware in development based on DO-254. In this webinar, we will introduce examples of common challenges often encountered during hardware verification, and more importantly, solutions to overcome these challenges.
To achieve a design that is not affected by metastability.
- ASIC
Webinar: The Necessity of CDC Verification in FPGA Design
This webinar will introduce the following topics for those interested in CDC (Clock Domain Crossing) verification in FPGA design. Webinar content: * What is a CDC issue? * Common approaches and considerations * Points to note about synchronizers in FPGA design * Solutions for CDC verification Additionally, for those interested, we will provide a one-month evaluation license for ALINT-PRO, a CDC/RDC verification solution offered by Aldec. We will also assist you in executing the verification. If you have struggled with CDC issues in the past or are looking to start CDC verification, please join us.
Equipped with the largest PolarFire and SmartFusion2 FPGAs on a single board, a first in the industry.
- ASIC
Aldec announces hardware-assisted RTL simulation acceleration for Microchip FPGA design.
The latest release of HES-DVM provides a simulation acceleration flow that significantly speeds up RTL simulation for designs targeting Microchip FPGA devices. Henderson, NV, USA – November 3, 2020 – Aldec, Inc. (hereinafter referred to as "Aldec"), a pioneer in HDL mixed-language simulation and hardware-assisted verification for FPGAs and ASICs, announced the HES-DVM simulation acceleration flow for Microchip Polarfire, SmartFusion2, and RTSX/RTAX FPGA designs using Aldec's HES-MPF500-M2S150 prototyping board. Please refer to the attached document for more details.
Industrial communication daughter card
- ASIC
- Board to Cable Connector
High-Speed Linked Daughter Card
- ASIC
- Board to Board Connectors
- Board to Cable Connector